From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
kvm@vger.kernel.org
Cc: anup@brainfault.org, atishp@atishpatra.org, palmer@dabbelt.com,
ajones@ventanamicro.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v3 0/3] RISC-V, KVM: add 'vlenb' and vector CSRs to get-reg-list
Date: Tue, 5 Dec 2023 14:45:06 -0300 [thread overview]
Message-ID: <20231205174509.2238870-1-dbarboza@ventanamicro.com> (raw)
Hi,
In this version we're exporting all vector regs, not just vector CSRs,
in get-reg-list. All changes were done in patch 3.
No other changes made.
Changes from v2:
- patch 3:
- check num_vector_regs() != 0 before copying vector regs
- export all 32 vector regs in num_vector_regs() and copy_vector_reg_indices()
- initialize 'size' out of the loop in copy_vector_reg_indices()
- v2 link: https://lore.kernel.org/kvm/20231205135041.2208004-1-dbarboza@ventanamicro.com/
Daniel Henrique Barboza (3):
RISC-V: KVM: set 'vlenb' in kvm_riscv_vcpu_alloc_vector_context()
RISC-V: KVM: add 'vlenb' Vector CSR
RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST
arch/riscv/kvm/vcpu_onereg.c | 55 ++++++++++++++++++++++++++++++++++++
arch/riscv/kvm/vcpu_vector.c | 16 +++++++++++
2 files changed, 71 insertions(+)
--
2.41.0
next reply other threads:[~2023-12-05 17:45 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-05 17:45 Daniel Henrique Barboza [this message]
2023-12-05 17:45 ` [PATCH v3 1/3] RISC-V: KVM: set 'vlenb' in kvm_riscv_vcpu_alloc_vector_context() Daniel Henrique Barboza
2023-12-05 17:45 ` [PATCH v3 2/3] RISC-V: KVM: add 'vlenb' Vector CSR Daniel Henrique Barboza
2023-12-05 17:45 ` [PATCH v3 3/3] RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST Daniel Henrique Barboza
2023-12-14 7:52 ` Andrew Jones
2023-12-14 5:30 ` [PATCH v3 0/3] RISC-V, KVM: add 'vlenb' and vector CSRs to get-reg-list Anup Patel
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