From: Dave Jiang <dave.jiang@intel.com>
To: Thomas Gleixner <tglx@linutronix.de>,
vkoul@kernel.org, megha.dey@intel.com, maz@kernel.org,
bhelgaas@google.com, alex.williamson@redhat.com,
jacob.jun.pan@intel.com, ashok.raj@intel.com, jgg@mellanox.com,
yi.l.liu@intel.com, baolu.lu@intel.com, kevin.tian@intel.com,
sanjay.k.kumar@intel.com, tony.luck@intel.com,
jing.lin@intel.com, dan.j.williams@intel.com,
kwankhede@nvidia.com, eric.auger@redhat.com, parav@mellanox.com,
rafael@kernel.org, netanelg@mellanox.com, shahafs@mellanox.com,
yan.y.zhao@linux.intel.com, pbonzini@redhat.com,
samuel.ortiz@intel.com, mona.hossain@intel.com
Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org,
x86@kernel.org, linux-pci@vger.kernel.org, kvm@vger.kernel.org
Subject: Re: [PATCH v3 05/18] dmaengine: idxd: add IMS support in base driver
Date: Thu, 1 Oct 2020 13:48:10 -0700 [thread overview]
Message-ID: <20743676-1e7e-5535-dcff-c5dadc7ee025@intel.com> (raw)
In-Reply-To: <87sgazgl0b.fsf@nanos.tec.linutronix.de>
On 9/30/2020 11:47 AM, Thomas Gleixner wrote:
> On Tue, Sep 15 2020 at 16:28, Dave Jiang wrote:
>> struct idxd_device {
>> @@ -170,6 +171,7 @@ struct idxd_device {
>>
>> int num_groups;
>>
>> + u32 ims_offset;
>> u32 msix_perm_offset;
>> u32 wqcfg_offset;
>> u32 grpcfg_offset;
>> @@ -177,6 +179,7 @@ struct idxd_device {
>>
>> u64 max_xfer_bytes;
>> u32 max_batch_size;
>> + int ims_size;
>> int max_groups;
>> int max_engines;
>> int max_tokens;
>> @@ -196,6 +199,7 @@ struct idxd_device {
>> struct work_struct work;
>>
>> int *int_handles;
>> + struct sbitmap ims_sbmap;
>
> This bitmap is needed for what?
Nothing anymore. I forgot to remove. All this is handled by MSI core now with
code from you.
>
>> --- a/drivers/dma/idxd/init.c
>> +++ b/drivers/dma/idxd/init.c
>> @@ -231,10 +231,51 @@ static void idxd_read_table_offsets(struct idxd_device *idxd)
>> idxd->msix_perm_offset = offsets.msix_perm * 0x100;
>> dev_dbg(dev, "IDXD MSIX Permission Offset: %#x\n",
>> idxd->msix_perm_offset);
>> + idxd->ims_offset = offsets.ims * 0x100;
>
> Magic constant pulled out of thin air. #define ....
Will fix
>
>> + dev_dbg(dev, "IDXD IMS Offset: %#x\n", idxd->ims_offset);
>> idxd->perfmon_offset = offsets.perfmon * 0x100;
>> dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset);
>> }
>>
>> +#define PCI_DEVSEC_CAP 0x23
>> +#define SIOVDVSEC1(offset) ((offset) + 0x4)
>> +#define SIOVDVSEC2(offset) ((offset) + 0x8)
>> +#define DVSECID 0x5
>> +#define SIOVCAP(offset) ((offset) + 0x14)
>> +
>> +static void idxd_check_siov(struct idxd_device *idxd)
>> +{
>> + struct pci_dev *pdev = idxd->pdev;
>> + struct device *dev = &pdev->dev;
>> + int dvsec;
>> + u16 val16;
>> + u32 val32;
>> +
>> + dvsec = pci_find_ext_capability(pdev, PCI_DEVSEC_CAP);
>> + pci_read_config_word(pdev, SIOVDVSEC1(dvsec), &val16);
>> + if (val16 != PCI_VENDOR_ID_INTEL) {
>> + dev_dbg(&pdev->dev, "DVSEC vendor id is not Intel\n");
>> + return;
>> + }
>> +
>> + pci_read_config_word(pdev, SIOVDVSEC2(dvsec), &val16);
>> + if (val16 != DVSECID) {
>> + dev_dbg(&pdev->dev, "DVSEC ID is not SIOV\n");
>> + return;
>> + }
>> +
>> + pci_read_config_dword(pdev, SIOVCAP(dvsec), &val32);
>> + if ((val32 & 0x1) && idxd->hw.gen_cap.max_ims_mult) {
>> + idxd->ims_size = idxd->hw.gen_cap.max_ims_mult * 256ULL;
>> + dev_dbg(dev, "IMS size: %u\n", idxd->ims_size);
>> + set_bit(IDXD_FLAG_SIOV_SUPPORTED, &idxd->flags);
>> + dev_dbg(&pdev->dev, "IMS supported for device\n");
>> + return;
>> + }
>> +
>> + dev_dbg(&pdev->dev, "SIOV unsupported for device\n");
>
> It's really hard to find the code inside all of this dev_dbg()
> noise. But why is this capability check done in this driver? Is this
> capability stuff really IDXD specific or is the next device which
> supports this going to copy and pasta the above?
Will look into move this into a common detection function for all similar
devices. This should be common for all Intel devices that support SIOV.
>
>> static void idxd_read_caps(struct idxd_device *idxd)
>> {
>> struct device *dev = &idxd->pdev->dev;
>> @@ -253,6 +294,7 @@ static void idxd_read_caps(struct idxd_device *idxd)
>> dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes);
>> idxd->max_batch_size = 1U << idxd->hw.gen_cap.max_batch_shift;
>> dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size);
>> + idxd_check_siov(idxd);
>> if (idxd->hw.gen_cap.config_en)
>> set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags);
>>
>> @@ -347,9 +389,19 @@ static int idxd_probe(struct idxd_device *idxd)
>>
>> idxd->major = idxd_cdev_get_major(idxd);
>>
>> + if (idxd->ims_size) {
>> + rc = sbitmap_init_node(&idxd->ims_sbmap, idxd->ims_size, -1,
>> + GFP_KERNEL, dev_to_node(dev));
>> + if (rc < 0)
>> + goto sbitmap_fail;
>> + }
>
> Ah, here the bitmap is allocated, but it's still completely unclear what
> it is used for.
Need to remove.
>
> The subject line is misleading as hell. This does not add support, it's
> doing some magic capability checks and allocates stuff which nobody
> knows what it is used for.
With the unneeded code removal and moving the SIOV detection code to common
implementation, it should be more clear.
>
> Thanks,
>
> tglx
>
>
next prev parent reply other threads:[~2020-10-01 20:48 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <160021207013.67751.8220471499908137671.stgit@djiang5-desk3.ch.intel.com>
2020-09-15 23:27 ` [PATCH v3 01/18] irqchip: Add IMS (Interrupt Message Storage) driver Dave Jiang
2020-09-30 18:23 ` Thomas Gleixner
2020-10-01 22:59 ` Dey, Megha
2020-09-15 23:27 ` [PATCH v3 02/18] iommu/vt-d: Add DEV-MSI support Dave Jiang
2020-09-30 18:32 ` Thomas Gleixner
2020-10-01 23:26 ` Dey, Megha
2020-10-02 11:13 ` Thomas Gleixner
2020-10-08 7:54 ` David Woodhouse
2020-10-20 21:42 ` Dey, Megha
2020-09-15 23:28 ` [PATCH v3 05/18] dmaengine: idxd: add IMS support in base driver Dave Jiang
2020-09-30 18:47 ` Thomas Gleixner
2020-09-30 18:51 ` Jason Gunthorpe
2020-09-30 21:48 ` Thomas Gleixner
2020-09-30 21:49 ` Raj, Ashok
2020-09-30 21:57 ` Thomas Gleixner
2020-10-01 1:07 ` Raj, Ashok
2020-10-01 8:44 ` Thomas Gleixner
2020-09-30 22:38 ` Jason Gunthorpe
2020-10-01 20:48 ` Dave Jiang [this message]
2020-09-15 23:28 ` [PATCH v3 07/18] dmaengine: idxd: add basic mdev registration and helper functions Dave Jiang
2020-09-15 23:28 ` [PATCH v3 10/18] dmaengine: idxd: virtual device commands emulation Dave Jiang
2020-09-15 23:28 ` [PATCH v3 12/18] dmaengine: idxd: add mdev type as a new wq type Dave Jiang
2020-09-15 23:29 ` [PATCH v3 13/18] dmaengine: idxd: add dedicated wq mdev type Dave Jiang
2020-09-15 23:29 ` [PATCH v3 14/18] dmaengine: idxd: add new wq state for mdev Dave Jiang
2020-09-15 23:29 ` [PATCH v3 15/18] dmaengine: idxd: add error notification from host driver to mediated device Dave Jiang
2020-09-15 23:29 ` [PATCH v3 16/18] dmaengine: idxd: add ABI documentation for mediated device support Dave Jiang
2020-09-17 15:06 ` [PATCH v3 00/18] Add VFIO mediated device support and DEV-MSI support for the idxd driver Jason Gunthorpe
2020-09-17 17:15 ` Dave Jiang
2020-09-17 17:27 ` Jason Gunthorpe
2020-09-17 17:30 ` Alex Williamson
2020-09-17 17:37 ` Jason Gunthorpe
[not found] ` <160021248280.67751.12525558281536923518.stgit@djiang5-desk3.ch.intel.com>
2020-09-30 18:36 ` [PATCH v3 04/18] dmaengine: idxd: add interrupt handle request support Thomas Gleixner
2020-10-01 20:16 ` Dave Jiang
[not found] ` <160021253189.67751.12686144284999931703.stgit@djiang5-desk3.ch.intel.com>
2020-09-30 19:57 ` [PATCH v3 11/18] dmaengine: idxd: ims setup for the vdcm Thomas Gleixner
2020-10-07 21:54 ` Dave Jiang
2020-10-08 7:39 ` Thomas Gleixner
2020-10-08 16:51 ` Dave Jiang
2020-10-08 23:17 ` Thomas Gleixner
2020-10-08 23:32 ` Jason Gunthorpe
2020-10-09 0:27 ` Dave Jiang
2020-10-09 1:22 ` Raj, Ashok
2020-10-09 11:57 ` Jason Gunthorpe
2020-10-09 12:43 ` Raj, Ashok
2020-10-09 12:49 ` Jason Gunthorpe
2020-10-09 13:02 ` Raj, Ashok
2020-10-09 13:12 ` Jason Gunthorpe
2020-10-09 13:40 ` Raj, Ashok
2020-10-09 14:44 ` Thomas Gleixner
2020-10-09 14:52 ` Jason Gunthorpe
2020-10-09 16:02 ` Thomas Gleixner
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