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charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BY5PR11MB4435.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d3770924-8fd7-428a-20aa-08d9c3e1b97d X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Dec 2021 17:54:09.4860 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: f57d+Ki4EmoRA2aPb+Wj/YT4Wvi0Xr51CtI944Wf5r2qmAA1UVmI9LpA7dWGbBAfdl4Wi2d+0oKgGpbIM4068A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB3030 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org > On Dec 10, 2021, at 2:13 PM, Paolo Bonzini wrote: >=20 > On 12/10/21 17:30, Paolo Bonzini wrote: >>>=20 >>> +static int kvm_vcpu_ioctl_x86_set_xsave2(struct kvm_vcpu *vcpu, u8 *st= ate) >>> +{ >>> + if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) >>> + return 0; >>> + >>> + return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu, state= , >>> + supported_xcr0, &vcpu->arch.pkru); >>> +} >>> + >> I think fpu_copy_uabi_to_guest_fpstate (and therefore copy_uabi_from_ker= nel_to_xstate) needs to check that the size is compatible with the componen= ts in the input. >> Also, IIUC the size of the AMX state will vary in different processors. = Is this correct? If so, this should be handled already by KVM_GET/SET_XS= AVE2 and therefore should be part of the arch/x86/kernel/fpu APIs. In the = future we want to support migrating a "small AMX" host to a "large AMX" hos= t; and also migrating from a "large AMX" host to a "small AMX" host if the = guest CPUID is compatible with the destination of the migration. >=20 > So, the size of the AMX state will depend on the active "palette" in TILE= CONFIG, and on the CPUID information. I have a few questions on how Intel = intends to handle future extensions to AMX: >=20 > - can we assume that, in the future, palette 1 will always have the same = value (bytes_per_row=3D64, max_names=3D8, max_rows=3D16), and basically tha= t the only variable value is really the number of palettes? >=20 > - how does Intel plan to handle bigger TILEDATA? Will it use more XCR0 b= its or will it rather enlarge save state 18? >=20 > If it will use more XCR0 bits, I suppose that XCR0 bits will control whic= h palettes can be chosen by LDTILECFG. >=20 > If not, on the other hand, this will be a first case of one system's XSAV= E data not being XRSTOR-able on another system even if the destination syst= em can set XCR0 to the same value as the source system. >=20 > Likewise, if the size and offsets for save state 18 were to vary dependin= g on the selected palette, then this would be novel, in that the save state= size and offsets would not be in CPUID anymore. It would be particularly = interesting for non-compacted format, where all save states after 18 would = also move forward. >=20 > So, I hope that save state 18 will be frozen to 8k. In that case, and if= palette 1 is frozen to the same values as today, implementing migration wi= ll not be a problem; it will be essentially the same as SSE->AVX (horizonta= l extension of existing registers) and/or AVX->AVX512 (both horizontal and = vertical extension). Hi Paolo, I would like to confirm that the state component 18 will remain 8KB and pal= ette 1 will remain the same.=20 Thanks, ---=20 Jun