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([2001:b07:6468:f312:e3ec:5559:7c5c:1928]) by smtp.googlemail.com with ESMTPSA id f18-20020a17090631d200b007336c3f05bdsm5638371ejf.178.2022.09.05.14.58.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 05 Sep 2022 14:58:15 -0700 (PDT) Message-ID: <38f5cb16-84d3-d50c-7a85-c4940f3ef319@redhat.com> Date: Mon, 5 Sep 2022 23:58:13 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.1 Subject: Re: [PATCH v2 01/23] KVM: x86: Purge "highest ISR" cache when updating APICv state Content-Language: en-US To: Sean Christopherson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Suravee Suthikulpanit , Maxim Levitsky , Li RongQing References: <20220903002254.2411750-1-seanjc@google.com> <20220903002254.2411750-2-seanjc@google.com> From: Paolo Bonzini In-Reply-To: <20220903002254.2411750-2-seanjc@google.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On 9/3/22 02:22, Sean Christopherson wrote: > Purge the "highest ISR" cache when updating APICv state on a vCPU. The > cache must not be used when APICv is active as hardware may emulate EOIs > (and other operations) without exiting to KVM. > > This fixes a bug where KVM will effectively block IRQs in perpetuity due > to the "highest ISR" never getting reset if APICv is activated on a vCPU > while an IRQ is in-service. Hardware emulates the EOI and KVM never gets > a chance to update its cache. > > Fixes: b26a695a1d78 ("kvm: lapic: Introduce APICv update helper function") > Cc: stable@vger.kernel.org > Cc: Suravee Suthikulpanit > Cc: Maxim Levitsky > Signed-off-by: Sean Christopherson > --- > arch/x86/kvm/lapic.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > index 9dda989a1cf0..38e9b8e5278c 100644 > --- a/arch/x86/kvm/lapic.c > +++ b/arch/x86/kvm/lapic.c > @@ -2429,6 +2429,7 @@ void kvm_apic_update_apicv(struct kvm_vcpu *vcpu) > */ > apic->isr_count = count_vectors(apic->regs + APIC_ISR); > } > + apic->highest_isr_cache = -1; > } > EXPORT_SYMBOL_GPL(kvm_apic_update_apicv); > > @@ -2485,7 +2486,6 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) > kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0); > } > kvm_apic_update_apicv(vcpu); > - apic->highest_isr_cache = -1; > update_divide_count(apic); > atomic_set(&apic->lapic_timer.pending, 0); > > @@ -2772,7 +2772,6 @@ int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) > __start_apic_timer(apic, APIC_TMCCT); > kvm_lapic_set_reg(apic, APIC_TMCCT, 0); > kvm_apic_update_apicv(vcpu); > - apic->highest_isr_cache = -1; > if (apic->apicv_active) { > static_call_cond(kvm_x86_apicv_post_state_restore)(vcpu); > static_call_cond(kvm_x86_hwapic_irr_update)(vcpu, apic_find_highest_irr(apic)); Reviewed-by: Paolo Bonzini