From: Auger Eric <eric.auger@redhat.com>
To: Marc Zyngier <maz@kernel.org>,
linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org
Cc: James Morse <james.morse@arm.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
kernel-team@android.com
Subject: Re: [PATCH v2 6/7] KVM: arm64: Upgrade PMU support to ARMv8.4
Date: Wed, 27 Jan 2021 18:53:23 +0100 [thread overview]
Message-ID: <56041147-0bd8-dbb2-d1ca-550f3db7f05d@redhat.com> (raw)
In-Reply-To: <20210125122638.2947058-7-maz@kernel.org>
Hi Marc,
On 1/25/21 1:26 PM, Marc Zyngier wrote:
> Upgrading the PMU code from ARMv8.1 to ARMv8.4 turns out to be
> pretty easy. All that is required is support for PMMIR_EL1, which
> is read-only, and for which returning 0 is a valid option as long
> as we don't advertise STALL_SLOT as an implemented event.
>
> Let's just do that and adjust what we return to the guest.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 3 +++
> arch/arm64/kvm/pmu-emul.c | 6 ++++++
> arch/arm64/kvm/sys_regs.c | 11 +++++++----
> 3 files changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 8b5e7e5c3cc8..2fb3f386588c 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -846,7 +846,10 @@
>
> #define ID_DFR0_PERFMON_SHIFT 24
>
> +#define ID_DFR0_PERFMON_8_0 0x3
> #define ID_DFR0_PERFMON_8_1 0x4
> +#define ID_DFR0_PERFMON_8_4 0x5
> +#define ID_DFR0_PERFMON_8_5 0x6
>
> #define ID_ISAR4_SWP_FRAC_SHIFT 28
> #define ID_ISAR4_PSR_M_SHIFT 24
> diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
> index 398f6df1bbe4..72cd704a8368 100644
> --- a/arch/arm64/kvm/pmu-emul.c
> +++ b/arch/arm64/kvm/pmu-emul.c
> @@ -795,6 +795,12 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1)
> base = 0;
> } else {
> val = read_sysreg(pmceid1_el0);
> + /*
> + * Don't advertise STALL_SLOT, as PMMIR_EL0 is handled
> + * as RAZ
> + */
> + if (vcpu->kvm->arch.pmuver >= ID_AA64DFR0_PMUVER_8_4)
> + val &= ~BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT - 32);
what about the STALL_SLOT_BACKEND and FRONTEND events then?
> base = 32;
> }
>
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 8f79ec1fffa7..5da536ab738d 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -1051,16 +1051,16 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
> /* Limit debug to ARMv8.0 */
> val &= ~FEATURE(ID_AA64DFR0_DEBUGVER);
> val |= FIELD_PREP(FEATURE(ID_AA64DFR0_DEBUGVER), 6);
> - /* Limit guests to PMUv3 for ARMv8.1 */
> + /* Limit guests to PMUv3 for ARMv8.4 */
> val = cpuid_feature_cap_perfmon_field(val,
> ID_AA64DFR0_PMUVER_SHIFT,
> - kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_1 : 0);
> + kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0);
> break;
> case SYS_ID_DFR0_EL1:
> - /* Limit guests to PMUv3 for ARMv8.1 */
> + /* Limit guests to PMUv3 for ARMv8.4 */
> val = cpuid_feature_cap_perfmon_field(val,
> ID_DFR0_PERFMON_SHIFT,
> - kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_1 : 0);
> + kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0);
> break;
> }
>
> @@ -1496,6 +1496,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
>
> { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
> { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
"KVM: arm64: Hide PMU registers from userspace when not available"
changed the above, doesn't it?
> + { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
>
> { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
> { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
> @@ -1918,6 +1919,8 @@ static const struct sys_reg_desc cp15_regs[] = {
> { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
> { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 4), access_pmceid },
> { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 5), access_pmceid },
> + /* PMMIR */
> + { Op1( 0), CRn( 9), CRm(14), Op2( 6), trap_raz_wi },
>
> /* PRRR/MAIR0 */
> { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
>
Thanks
Eric
next prev parent reply other threads:[~2021-01-27 17:55 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-25 12:26 [PATCH v2 0/7] KVM: arm64: More PMU/debug ID register fixes Marc Zyngier
2021-01-25 12:26 ` [PATCH v2 1/7] KVM: arm64: Fix missing RES1 in emulation of DBGBIDR Marc Zyngier
2021-01-26 17:32 ` Alexandru Elisei
2021-01-25 12:26 ` [PATCH v2 2/7] KVM: arm64: Fix AArch32 PMUv3 capping Marc Zyngier
2021-01-26 17:35 ` Alexandru Elisei
2021-01-25 12:26 ` [PATCH v2 3/7] KVM: arm64: Add handling of AArch32 PCMEID{2,3} PMUv3 registers Marc Zyngier
2021-01-25 12:26 ` [PATCH v2 4/7] KVM: arm64: Refactor filtering of ID registers Marc Zyngier
2021-01-27 12:12 ` Alexandru Elisei
2021-01-25 12:26 ` [PATCH v2 5/7] KVM: arm64: Limit the debug architecture to ARMv8.0 Marc Zyngier
2021-01-27 12:18 ` Alexandru Elisei
2021-01-25 12:26 ` [PATCH v2 6/7] KVM: arm64: Upgrade PMU support to ARMv8.4 Marc Zyngier
2021-01-27 14:09 ` Alexandru Elisei
2021-01-27 14:35 ` Marc Zyngier
2021-01-27 17:00 ` Alexandru Elisei
2021-01-27 17:23 ` Marc Zyngier
2021-01-27 17:41 ` Alexandru Elisei
2021-02-03 10:32 ` Marc Zyngier
2021-02-03 17:29 ` Alexandru Elisei
2021-01-27 17:53 ` Auger Eric [this message]
2021-02-03 10:36 ` Marc Zyngier
2021-02-03 11:07 ` Auger Eric
2021-02-03 11:20 ` Marc Zyngier
2021-02-03 12:39 ` Auger Eric
2021-02-03 13:28 ` Marc Zyngier
2021-02-04 12:32 ` Alexandru Elisei
2021-02-04 14:21 ` Marc Zyngier
2021-01-25 12:26 ` [PATCH v2 7/7] KVM: arm64: Use symbolic names for the PMU versions Marc Zyngier
2021-01-27 14:28 ` Alexandru Elisei
2021-01-27 17:56 ` Auger Eric
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