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([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.gmail.com with ESMTPSA id q4sm570488ejx.8.2021.01.27.01.48.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Jan 2021 01:48:52 -0800 (PST) Subject: Re: [RESEND v13 03/10] KVM: x86/pmu: Use IA32_PERF_CAPABILITIES to adjust features visibility To: Like Xu Cc: Ingo Molnar , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , ak@linux.intel.com, wei.w.wang@intel.com, kan.liang@intel.com, x86@kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Joerg Roedel , Jim Mattson , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li References: <20210108013704.134985-1-like.xu@linux.intel.com> <20210108013704.134985-4-like.xu@linux.intel.com> From: Paolo Bonzini Message-ID: <5da57047-db15-adb6-f3bc-6152753d0b49@redhat.com> Date: Wed, 27 Jan 2021 10:48:50 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On 27/01/21 07:04, Like Xu wrote: > On 2021/1/26 17:42, Paolo Bonzini wrote: >> On 08/01/21 02:36, Like Xu wrote: >>> >>> @@ -401,6 +398,9 @@ static void intel_pmu_init(struct kvm_vcpu *vcpu) >>>          pmu->fixed_counters[i].idx = i + INTEL_PMC_IDX_FIXED; >>>          pmu->fixed_counters[i].current_config = 0; >>>      } >>> + >>> +    vcpu->arch.perf_capabilities = guest_cpuid_has(vcpu, >>> X86_FEATURE_PDCM) ? >>> +        vmx_get_perf_capabilities() : 0; >> >> There is one thing I don't understand with this patch: intel_pmu_init >> is not called when CPUID is changed.  So I would have thought that >> anything that uses guest_cpuid_has must stay in intel_pmu_refresh.  As >> I understand it vcpu->arch.perf_capabilities is always set to 0 >> (vmx_get_perf_capabilities is never called), and kvm_set_msr_common >> would fail to set any bit in the MSR.  What am I missing? >> >> In addition, the code of patch 4: >> >> +    if (!intel_pmu_lbr_is_enabled(vcpu)) { >> +        vcpu->arch.perf_capabilities &= ~PMU_CAP_LBR_FMT; >> +        lbr_desc->records.nr = 0; >> +    } >> >> is not okay after MSR changes.  The value written by the host must be >> either rejected (with "return 1") or applied unchanged. >> >> Fortunately I think this code is dead if you move the check in >> kvm_set_msr from patch 9 to patch 4.  However, in patch 9 >> vmx_get_perf_capabilities() must only set the LBR format bits if >> intel_pmu_lbr_is_compatible(vcpu). > > Thanks for the guidance. How about handling it in this way: > > In the intel_pmu_init(): > >     vcpu->arch.perf_capabilities = 0; >     lbr_desc->records.nr = 0; > > In the intel_pmu_refresh(): > >     if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) { >         vcpu->arch.perf_capabilities = vmx_get_perf_capabilities(); >         if (!lbr_desc->records.nr) >             vcpu->arch.perf_capabilities &= ~PMU_CAP_LBR_FMT; >     } > > In the vmx_set_msr(): > >     case MSR_IA32_PERF_CAPABILITIES: >         // set up lbr_desc->records.nr >         if (!intel_pmu_lbr_is_compatible(vcpu)) Maybe pass msr_info.data to intel_pmu_lbr_is_compatible? Otherwise seems okay, thanks Like. Paolo