Re: [kvm-unit-tests PATCH 18/18] arm: cstart64.S: Remove icache invalidation from asm_mmu_enable

[Alexandru Elisei <alexandru.elisei@arm.com>]

Hi,

On 11/27/19 2:24 PM, Alexandru Elisei wrote:
> According to the ARM ARM [1]:
>
> "In Armv8, any permitted instruction cache implementation can be
> described as implementing the IVIPT Extension to the Arm architecture.
>
> The formal definition of the Arm IVIPT Extension is that it reduces the
> instruction cache maintenance requirement to the following condition:
> Instruction cache maintenance is required only after writing new data to
> a PA that holds an instruction".

And immediately following: "Previous versions of the Arm architecture have
permitted an instruction cache option that does not implement the Arm IVIPT
Extension".

That type of cache is the ASID and VMID tagged VIVT instruction cache [1], which
require icache maintenance when the instruction at a given virtual address
changes. Seeing how we don't change the IPA for the same VA anywhere in
kvm-unit-tests, I propose that it will be up to the person who will write such a
test to use the appropriate maintenance operations.

[1] ARM DDI 0406C.d, section B3.11.2.

Thanks,
Alex
> We never patch instructions in the boot path, so remove the icache
> invalidation from asm_mmu_enable. Tests that modify instructions (like
> the cache test) should have their own icache maintenance operations.
>
> [1] ARM DDI 0487E.a, section D5.11.2 "Instruction caches"
>
> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
> ---
>  arm/cstart64.S | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/arm/cstart64.S b/arm/cstart64.S
> index 87bf873795a1..7e7f8b2e8f0b 100644
> --- a/arm/cstart64.S
> +++ b/arm/cstart64.S
> @@ -166,7 +166,6 @@ halt:
>  
>  .globl asm_mmu_enable
>  asm_mmu_enable:
> -	ic	iallu			// I+BTB cache invalidate
>  	tlbi	vmalle1			// invalidate I + D TLBs
>  	dsb	nsh
>