Re: [PATCH] KVM: arm64: Allow in-atomic injection of SPIs

[Zenghui Yu <yuzenghui@huawei.com>]

Hi Marc,

On 2020/5/27 15:55, Marc Zyngier wrote:
> Hi Zenghui,
> 
> On 2020-05-27 08:41, Zenghui Yu wrote:
>> On 2020/5/27 0:11, Marc Zyngier wrote:
>>> On a system that uses SPIs to implement MSIs (as it would be
>>> the case on a GICv2 system exposing a GICv2m to its guests),
>>> we deny the possibility of injecting SPIs on the in-atomic
>>> fast-path.
>>>
>>> This results in a very large amount of context-switches
>>> (roughly equivalent to twice the interrupt rate) on the host,
>>> and suboptimal performance for the guest (as measured with
>>> a test workload involving a virtio interface backed by vhost-net).
>>> Given that GICv2 systems are usually on the low-end of the spectrum
>>> performance wise, they could do without the aggravation.
>>>
>>> We solved this for GICv3+ITS by having a translation cache. But
>>> SPIs do not need any extra infrastructure, and can be immediately
>>> injected in the virtual distributor as the locking is already
>>> heavy enough that we don't need to worry about anything.
>>>
>>> This halves the number of context switches for the same workload.
>>>
>>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>>> ---
>>>   arch/arm64/kvm/vgic/vgic-irqfd.c | 20 ++++++++++++++++----
>>>   arch/arm64/kvm/vgic/vgic-its.c   |  3 +--
>>>   2 files changed, 17 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/arch/arm64/kvm/vgic/vgic-irqfd.c 
>>> b/arch/arm64/kvm/vgic/vgic-irqfd.c
>>> index d8cdfea5cc96..11a9f81115ab 100644
>>> --- a/arch/arm64/kvm/vgic/vgic-irqfd.c
>>> +++ b/arch/arm64/kvm/vgic/vgic-irqfd.c
>>> @@ -107,15 +107,27 @@ int kvm_arch_set_irq_inatomic(struct 
>>> kvm_kernel_irq_routing_entry *e,
>>>                     struct kvm *kvm, int irq_source_id, int level,
>>>                     bool line_status)
>>
>> ... and you may also need to update the comment on top of it to
>> reflect this change.
>>
>> /**
>>  * kvm_arch_set_irq_inatomic: fast-path for irqfd injection
>>  *
>>  * Currently only direct MSI injection is supported.
>>  */
> 
> As far as I can tell, it is still valid (at least from the guest's
> perspective). You could in practice use that to deal with level
> interrupts, but we only inject the rising edge on this path, never
> the falling edge. So effectively, this is limited to edge interrupts,
> which is mostly MSIs.

Oops... I had wrongly mixed MSI with the architecture-defined LPI, and
was think that we should add something like "direct SPI injection is
also supported now". Sorry.

> 
> Unless you are thinking of something else which I would have missed?

No, please ignore the noisy.


Thanks,
Zenghui