From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 389E6C83000 for ; Tue, 28 Apr 2020 08:10:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1D2F0206E2 for ; Tue, 28 Apr 2020 08:10:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726853AbgD1IKa (ORCPT ); Tue, 28 Apr 2020 04:10:30 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:18250 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726377AbgD1IK3 (ORCPT ); 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Tue, 28 Apr 2020 08:10:25 +0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06avi18878370.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 03S8ANMu35586342 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 28 Apr 2020 08:10:23 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AEA5C52059; Tue, 28 Apr 2020 08:10:23 +0000 (GMT) Received: from oc3016276355.ibm.com (unknown [9.145.156.174]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 636B65204F; Tue, 28 Apr 2020 08:10:23 +0000 (GMT) Subject: Re: [kvm-unit-tests PATCH v6 02/10] s390x: Use PSW bits definitions in cstart To: David Hildenbrand , kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, thuth@redhat.com, cohuck@redhat.com References: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> <1587725152-25569-3-git-send-email-pmorel@linux.ibm.com> <231839f0-41f9-844c-efc4-34893e7b720f@redhat.com> From: Pierre Morel Message-ID: <6bc4a268-e4c4-d9f0-1e4a-94c48a081c10@linux.ibm.com> Date: Tue, 28 Apr 2020 10:10:23 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <231839f0-41f9-844c-efc4-34893e7b720f@redhat.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-04-28_03:2020-04-27,2020-04-28 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 spamscore=0 malwarescore=0 adultscore=0 suspectscore=0 mlxlogscore=999 impostorscore=0 lowpriorityscore=0 mlxscore=0 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004280065 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On 2020-04-27 11:01, David Hildenbrand wrote: > On 24.04.20 12:45, Pierre Morel wrote: >> This patch defines the PSW bits EA/BA used to initialize the PSW masks >> for exceptions. >> >> Since some PSW mask definitions exist already in arch_def.h we add these >> definitions there. >> We move all PSW definitions together and protect assembler code against >> C syntax. >> >> Signed-off-by: Pierre Morel >> --- >> lib/s390x/asm/arch_def.h | 16 ++++++++++++---- >> s390x/cstart64.S | 15 ++++++++------- >> 2 files changed, 20 insertions(+), 11 deletions(-) >> >> diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h >> index 15a4d49..c54409a 100644 >> --- a/lib/s390x/asm/arch_def.h >> +++ b/lib/s390x/asm/arch_def.h >> @@ -10,15 +10,22 @@ >> #ifndef _ASM_S390X_ARCH_DEF_H_ >> #define _ASM_S390X_ARCH_DEF_H_ >> >> +#define PSW_MASK_EXT 0x0100000000000000UL >> +#define PSW_MASK_DAT 0x0400000000000000UL >> +#define PSW_MASK_SHORT_PSW 0x0008000000000000UL >> +#define PSW_MASK_PSTATE 0x0001000000000000UL >> +#define PSW_MASK_BA 0x0000000080000000UL >> +#define PSW_MASK_EA 0x0000000100000000UL >> + >> +#define PSW_EXCEPTION_MASK (PSW_MASK_EA | PSW_MASK_BA) >> +#define PSW_RESET_MASK (PSW_EXCEPTION_MASK | PSW_MASK_SHORT_PSW) >> + >> +#ifndef __ASSEMBLER__ >> struct psw { >> uint64_t mask; >> uint64_t addr; >> }; >> >> -#define PSW_MASK_EXT 0x0100000000000000UL >> -#define PSW_MASK_DAT 0x0400000000000000UL >> -#define PSW_MASK_PSTATE 0x0001000000000000UL >> - >> #define CR0_EXTM_SCLP 0X0000000000000200UL >> #define CR0_EXTM_EXTC 0X0000000000002000UL >> #define CR0_EXTM_EMGC 0X0000000000004000UL >> @@ -297,4 +304,5 @@ static inline uint32_t get_prefix(void) >> return current_prefix; >> } >> >> +#endif /* __ASSEMBLER */ >> #endif >> diff --git a/s390x/cstart64.S b/s390x/cstart64.S >> index ba2e67c..e394b3a 100644 >> --- a/s390x/cstart64.S >> +++ b/s390x/cstart64.S >> @@ -12,6 +12,7 @@ >> */ >> #include >> #include >> +#include >> >> .section .init >> >> @@ -225,19 +226,19 @@ svc_int: >> >> .align 8 >> reset_psw: >> - .quad 0x0008000180000000 >> + .quad PSW_RESET_MASK > > I'd really prefer > > .quad PSW_EXCEPTION_MASK | PSW_MASK_SHORT_PSW > > here instead and drop PSW_RESET_MASK. Makes it clearer that we are > talking about a special short psw here. > > Apart from that, looks good to me. > > Thanks, I will do as you propose, Regards, Pierre -- Pierre Morel IBM Lab Boeblingen