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([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.gmail.com with ESMTPSA id v14sm166212edx.5.2021.05.04.01.06.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 May 2021 01:06:48 -0700 (PDT) Subject: Re: [PATCH v3 2/2] KVM: X86: Introduce KVM_HC_PAGE_ENC_STATUS hypercall To: Steve Rutherford Cc: Sean Christopherson , LKML , KVM list , Joerg Roedel , Brijesh Singh , Tom Lendacky , Ashish Kalra , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Borislav Petkov , X86 ML References: <20210429104707.203055-1-pbonzini@redhat.com> <20210429104707.203055-3-pbonzini@redhat.com> From: Paolo Bonzini Message-ID: <7c8f388c-1c0e-1fa8-24a5-46ffd40f8b24@redhat.com> Date: Tue, 4 May 2021 10:06:47 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On 04/05/21 01:22, Steve Rutherford wrote: > As far as I know, because of MSR filtering, the only "code" that needs > to be in KVM for MSR handling is a #define reserving the PV feature > number and a #define for the MSR number. > > Arguably, you don't even need to add the new PV bits to the supported > cpuid, since MSR filtering is really what determines if kernel support > is present. Not only I don't need to do that, I must not. :) >> At this point I very much prefer the latter, which is basically Ashish's >> earlier patch. > > The minor distinction would be that if you expose the cpuid bit to the > guest you plan on intercepting the MSR with filters, and would not > need any handler code in the kernel. Yep, and it's not a minor distinction after all (especially from the PoV of the guy who actually ends up maintaining the code, i.e. me), so that's what I'm going for. Paolo