From: "Xu, Like" <like.xu@intel.com>
To: Sean Christopherson <seanjc@google.com>,
Paolo Bonzini <pbonzini@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
wei.w.wang@intel.com, kvm@vger.kernel.org, x86@kernel.org,
linux-kernel@vger.kernel.org, Like Xu <like.xu@linux.intel.com>
Subject: Re: [PATCH v3 9/9] KVM: x86: Add XSAVE Support for Architectural LBRs
Date: Fri, 5 Mar 2021 10:57:05 +0800 [thread overview]
Message-ID: <860c429d-c0d8-fae6-955d-dd8560f2f9c5@intel.com> (raw)
In-Reply-To: <YEELZUP3BjStSvHq@google.com>
On 2021/3/5 0:31, Sean Christopherson wrote:
> Paolo, any thoughts on how to keep supported_xss aligned with support_xcr0,
> without spreading the logic around too much?
From 58be4152ced441395dfc439f446c5ad53bd48576 Mon Sep 17 00:00:00 2001
From: Like Xu <like.xu@linux.intel.com>
Date: Thu, 4 Mar 2021 13:21:38 +0800
Subject: [PATCH] KVM: x86: Refine the matching and clearing logic for
supported_xss
"The existing clearing of supported_xss here is pointless".
Let's refine the code path in this way: initialize the supported_xss
with the filter of KVM_SUPPORTED_XSS mask and update its value in
a bit clear manner (rather than bit setting).
Before:
(1) kvm_arch_hardware_setup
if (boot_cpu_has(X86_FEATURE_XSAVES))
rdmsrl(MSR_IA32_XSS, host_xss);
if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
supported_xss = 0;
else supported_xss &= host_xss;
(2) vmx_set_cpu_caps
supported_xss = 0;
if (!cpu_has_vmx_xsaves())
kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
else set available bits to supported_xss
After:
(1) kvm_arch_init
if (boot_cpu_has(X86_FEATURE_XSAVES))
rdmsrl(MSR_IA32_XSS, host_xss);
supported_xss = host_xss & KVM_SUPPORTED_XSS;
(2) vmx_set_cpu_caps
if (!cpu_has_vmx_xsaves())
kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
supported_xss = 0;
else clear un-available bits for supported_xss
Suggested-by: Sean Christopherson <seanjc@google.com>
Original-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
---
arch/x86/kvm/vmx/vmx.c | 5 +++--
arch/x86/kvm/x86.c | 13 +++++++------
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 4bc4bb49aaa9..8706323547c4 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -7288,9 +7288,10 @@ static __init void vmx_set_cpu_caps(void)
kvm_cpu_cap_set(X86_FEATURE_UMIP);
/* CPUID 0xD.1 */
- supported_xss = 0;
- if (!cpu_has_vmx_xsaves())
+ if (!cpu_has_vmx_xsaves()) {
kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
+ supported_xss = 0;
+ }
/* CPUID 0x80000001 */
if (!cpu_has_vmx_rdtscp())
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index d773836ceb7a..99cb62035bb2 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -205,6 +205,8 @@ static struct kvm_user_return_msrs __percpu
*user_return_msrs;
| XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
| XFEATURE_MASK_PKRU)
+#define KVM_SUPPORTED_XSS 0
+
u64 __read_mostly host_efer;
EXPORT_SYMBOL_GPL(host_efer);
@@ -8046,6 +8048,11 @@ int kvm_arch_init(void *opaque)
supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
}
+ if (boot_cpu_has(X86_FEATURE_XSAVES)) {
+ rdmsrl(MSR_IA32_XSS, host_xss);
+ supported_xss = host_xss & KVM_SUPPORTED_XSS;
+ }
+
if (pi_inject_timer == -1)
pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
#ifdef CONFIG_X86_64
@@ -10421,9 +10428,6 @@ int kvm_arch_hardware_setup(void *opaque)
rdmsrl_safe(MSR_EFER, &host_efer);
- if (boot_cpu_has(X86_FEATURE_XSAVES))
- rdmsrl(MSR_IA32_XSS, host_xss);
-
r = ops->hardware_setup();
if (r != 0)
return r;
@@ -10431,9 +10435,6 @@ int kvm_arch_hardware_setup(void *opaque)
memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
kvm_ops_static_call_update();
- if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
- supported_xss = 0;
-
#define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
#undef __kvm_cpu_cap_has
--
2.29.2
next prev parent reply other threads:[~2021-03-05 2:57 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-03 13:57 [PATCH v3 0/9] KVM: x86/pmu: Guest Architectural LBR Enabling Like Xu
2021-03-03 13:57 ` [PATCH v3 1/9] perf/x86/intel: Fix a comment about guest LBR support Like Xu
2021-03-03 16:49 ` Sean Christopherson
2021-03-03 13:57 ` [PATCH v3 2/9] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers Like Xu
2021-03-03 13:57 ` [PATCH v3 3/9] perf/x86/lbr: Skip checking for the existence of LBR_TOS for Arch LBR Like Xu
2021-03-03 13:57 ` [PATCH v3 4/9] perf/x86/lbr: Use GFP_ATOMIC for cpuc->lbr_xsave memory allocation Like Xu
2021-03-03 13:57 ` [PATCH v3 5/9] KVM: vmx/pmu: Add MSR_ARCH_LBR_DEPTH emulation for Arch LBR Like Xu
2021-03-03 16:58 ` Sean Christopherson
2021-03-04 2:30 ` Xu, Like
2021-03-04 16:12 ` Sean Christopherson
2021-03-05 2:33 ` Xu, Like
2021-03-03 13:57 ` [PATCH v3 6/9] KVM: vmx/pmu: Add MSR_ARCH_LBR_CTL " Like Xu
2021-03-03 17:19 ` Sean Christopherson
2021-03-04 2:58 ` Xu, Like
2021-03-04 16:25 ` Sean Christopherson
2021-03-03 13:57 ` [PATCH v3 7/9] KVM: vmx/pmu: Add Arch LBR emulation and its VMCS field Like Xu
2021-03-03 17:26 ` Sean Christopherson
2021-03-04 3:02 ` Xu, Like
2021-03-04 17:23 ` Sean Christopherson
2021-03-05 6:35 ` Xu, Like
2021-03-03 13:57 ` [PATCH v3 8/9] KVM: x86: Expose Architectural LBR CPUID leaf Like Xu
2021-03-03 17:34 ` Sean Christopherson
2021-03-03 18:01 ` Sean Christopherson
2021-03-03 13:57 ` [PATCH v3 9/9] KVM: x86: Add XSAVE Support for Architectural LBRs Like Xu
2021-03-03 18:03 ` Sean Christopherson
2021-03-04 3:43 ` Like Xu
2021-03-04 16:31 ` Sean Christopherson
2021-03-05 2:57 ` Xu, Like [this message]
2021-03-03 13:57 ` [kvm-unit-tests PATCH] x86: Update guest LBR tests for Architectural LBR Like Xu
2021-03-03 18:05 ` Sean Christopherson
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