From: Marc Zyngier <marc.zyngier@arm.com>
To: Will Deacon <will.deacon@arm.com>
Cc: kvm@vger.kernel.org, Catalin Marinas <catalin.marinas@arm.com>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 0/8] Workaround for Cortex-A76 erratum 1165522
Date: Tue, 04 Dec 2018 10:43:31 +0000 [thread overview]
Message-ID: <867egpd12k.wl-marc.zyngier@arm.com> (raw)
In-Reply-To: <20181203192242.GE29028@arm.com>
Hi Will,
On Mon, 03 Dec 2018 19:22:43 +0000,
Will Deacon <will.deacon@arm.com> wrote:
>
> Hi Marc,
>
> On Fri, Nov 23, 2018 at 06:40:59PM +0000, Marc Zyngier wrote:
> > Early Cortex-A76 suffer from an erratum that can result in invalid
> > TLBs when the CPU speculatively executes an AT instruction in the
> > middle of a guest world switch, while the guest virtual memory
> > configuration is in an inconsistent state.
> >
> > We handle this issue by mandating the use of VHE and making sure that
> > the guest context is fully installed before switching HCR_EL2.TGE to
> > zero. This ensures that a speculated AT instruction is either executed
> > on the host context (TGE set) or the guest context (TGE clear), and
> > that there is no intermediate state.
> >
> > There is some additional complexity in the TLB invalidation code,
> > where we most make sure that a speculated AT instruction cannot mess
> > the stage-1 TLBs.
>
> With James' ISB comments addressed, this looks pretty good to me. What's
> your plan for merging it? It's definitely going to conflict with the
> arm64 patch queue and last time that happened Paolo got irritated with us.
I'm pretty happy for the whole thing to go via the arm64 tree if
you're happy to take it directly.
I'll respin the series to address James comments shortly.
Thanks,
M.
--
Jazz is not dead, it just smell funny.
prev parent reply other threads:[~2018-12-04 10:43 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-23 18:40 [PATCH v2 0/8] Workaround for Cortex-A76 erratum 1165522 Marc Zyngier
2018-11-23 18:41 ` [PATCH v2 1/8] arm64: KVM: Make VHE Stage-2 TLB invalidation operations non-interruptible Marc Zyngier
2018-11-23 18:41 ` [PATCH v2 2/8] KVM: arm64: Rework detection of SVE, !VHE systems Marc Zyngier
2018-11-23 18:41 ` [PATCH v2 3/8] arm64: KVM: Install stage-2 translation before enabling traps Marc Zyngier
2018-11-23 18:41 ` [PATCH v2 4/8] arm64: Add TCR_EPD{0,1} definitions Marc Zyngier
2018-11-23 18:41 ` [PATCH v2 5/8] arm64: KVM: Force VHE for systems affected by erratum 1165522 Marc Zyngier
2018-11-23 18:41 ` [PATCH v2 6/8] arm64: KVM: Add synchronization on translation regime change for " Marc Zyngier
2018-11-27 9:51 ` James Morse
2018-11-23 18:41 ` [PATCH v2 7/8] arm64: KVM: Handle ARM erratum 1165522 in TLB invalidation Marc Zyngier
2018-11-27 9:50 ` James Morse
2018-12-06 17:21 ` Marc Zyngier
2018-11-23 18:41 ` [PATCH v2 8/8] arm64: Add configuration/documentation for Cortex-A76 erratum 1165522 Marc Zyngier
2018-12-03 19:22 ` [PATCH v2 0/8] Workaround " Will Deacon
2018-12-04 10:43 ` Marc Zyngier [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=867egpd12k.wl-marc.zyngier@arm.com \
--to=marc.zyngier@arm.com \
--cc=catalin.marinas@arm.com \
--cc=kvm@vger.kernel.org \
--cc=kvmarm@lists.cs.columbia.edu \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).