From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D292C2D0C0 for ; Sun, 22 Dec 2019 10:34:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 023992070A for ; Sun, 22 Dec 2019 10:34:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1577010893; bh=8mLWcC+lPFwoyj8oc2V0lIZ8hi8rjrhtfZxtSPNEOYA=; h=Date:From:To:Cc:Subject:In-Reply-To:References:List-ID:From; b=LwMS0xd24pChmWwcv3dJ2CUOa6eLzlYSvYaA5MPn/CCf3BhgWzZJCEPX5YBDr02UG ygP5EH3+iEgSGX62tO+WwgE0gDS1yg/5yPKqR+GM4pXlAj2TLaaTDDkTXjyFYT3mS9 DcPwt/Ii3BeI2oXx+ZYWrqsGYfCulbUiG12dJNB4= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726705AbfLVKet (ORCPT ); Sun, 22 Dec 2019 05:34:49 -0500 Received: from inca-roads.misterjones.org ([213.251.177.50]:46535 "EHLO inca-roads.misterjones.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725977AbfLVKes (ORCPT ); Sun, 22 Dec 2019 05:34:48 -0500 Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=big-swifty.misterjones.org) by cheepnis.misterjones.org with esmtpsa (TLSv1.2:AES256-GCM-SHA384:256) (Exim 4.80) (envelope-from ) id 1iiyZR-0005Mb-ML; Sun, 22 Dec 2019 11:34:45 +0100 Date: Sun, 22 Dec 2019 10:34:55 +0000 Message-ID: <86d0cgir74.wl-maz@kernel.org> From: Marc Zyngier To: Andrew Murray Cc: Catalin Marinas , Will Deacon , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 10/18] arm64: KVM/debug: use EL1&0 stage 1 translation regime In-Reply-To: <20191220143025.33853-11-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> <20191220143025.33853-11-andrew.murray@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: andrew.murray@arm.com, catalin.marinas@arm.com, will@kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, sudeep.holla@arm.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on cheepnis.misterjones.org); SAEximRunCond expanded to false Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Fri, 20 Dec 2019 14:30:17 +0000, Andrew Murray wrote: > > From: Sudeep Holla > > Now that we have all the save/restore mechanism in place, lets enable > the translation regime used by buffer from EL2 stage 1 to EL1 stage 1 > on VHE systems. > > Signed-off-by: Sudeep Holla > [ Reword commit, don't trap to EL2 ] Not trapping to EL2 for the case where we don't allow SPE in the guest is not acceptable. > Signed-off-by: Andrew Murray > --- > arch/arm64/kvm/hyp/switch.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c > index 67b7c160f65b..6c153b79829b 100644 > --- a/arch/arm64/kvm/hyp/switch.c > +++ b/arch/arm64/kvm/hyp/switch.c > @@ -100,6 +100,7 @@ static void activate_traps_vhe(struct kvm_vcpu *vcpu) > > write_sysreg(val, cpacr_el1); > > + write_sysreg(vcpu->arch.mdcr_el2 | 3 << MDCR_EL2_E2PB_SHIFT, mdcr_el2); > write_sysreg(kvm_get_hyp_vector(), vbar_el1); > } > NOKPROBE_SYMBOL(activate_traps_vhe); > @@ -117,6 +118,7 @@ static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu) > __activate_traps_fpsimd32(vcpu); > } > > + write_sysreg(vcpu->arch.mdcr_el2 | 3 << MDCR_EL2_E2PB_SHIFT, mdcr_el2); There is a _MASK macro that can replace this '3', and is in keeping with the rest of the code. It still remains that it looks like the wrong place to do this, and vcpu_load seems much better. Why should you write to mdcr_el2 on each entry to the guest, since you know whether it has SPE enabled at the point where it gets scheduled? M. -- Jazz is not dead, it just smells funny.