From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1DD9C433F5 for ; Thu, 18 Nov 2021 10:15:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 99B6461B73 for ; Thu, 18 Nov 2021 10:15:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244908AbhKRKSe (ORCPT ); Thu, 18 Nov 2021 05:18:34 -0500 Received: from mail.kernel.org ([198.145.29.99]:59242 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244800AbhKRKQb (ORCPT ); Thu, 18 Nov 2021 05:16:31 -0500 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 471E661B7D; Thu, 18 Nov 2021 10:13:31 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mneQ5-006Hod-7k; Thu, 18 Nov 2021 10:13:29 +0000 Date: Thu, 18 Nov 2021 10:13:28 +0000 Message-ID: <87mtm17ovr.wl-maz@kernel.org> From: Marc Zyngier To: Anup Patel Cc: Will Deacon , julien.thierry.kdev@gmail.com, Paolo Bonzini , Atish Patra , Alistair Francis , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Vincent Chen Subject: Re: [PATCH v10 kvmtool 5/8] riscv: Add PLIC device emulation In-Reply-To: <20211116052130.173679-6-anup.patel@wdc.com> References: <20211116052130.173679-1-anup.patel@wdc.com> <20211116052130.173679-6-anup.patel@wdc.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: anup.patel@wdc.com, will@kernel.org, julien.thierry.kdev@gmail.com, pbonzini@redhat.com, atishp@atishpatra.org, Alistair.Francis@wdc.com, anup@brainfault.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, vincent.chen@sifive.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Tue, 16 Nov 2021 05:21:27 +0000, Anup Patel wrote: > > The PLIC (platform level interrupt controller) manages peripheral > interrupts in RISC-V world. The per-CPU interrupts are managed > using CPU CSRs hence virtualized in-kernel by KVM RISC-V. > > This patch adds PLIC device emulation for KVMTOOL RISC-V. > > Signed-off-by: Vincent Chen > [For PLIC context CLAIM register emulation] > Signed-off-by: Anup Patel > --- > Makefile | 1 + > riscv/include/kvm/kvm-arch.h | 2 + > riscv/irq.c | 4 +- > riscv/plic.c | 518 +++++++++++++++++++++++++++++++++++ > 4 files changed, 523 insertions(+), 2 deletions(-) > create mode 100644 riscv/plic.c > [...] > +static void plic__context_write(struct plic_state *s, > + struct plic_context *c, > + u64 offset, void *data) > +{ > + u32 val; > + bool irq_update = false; > + > + mutex_lock(&c->irq_lock); > + > + switch (offset) { > + case CONTEXT_THRESHOLD: > + val = ioport__read32(data); > + val &= ((1 << PRIORITY_PER_ID) - 1); > + if (val <= s->max_prio) > + c->irq_priority_threshold = val; > + else > + irq_update = true; > + break; > + case CONTEXT_CLAIM: > + val = ioport__read32(data); > + if (val < plic.num_irq) { > + c->irq_claimed[val / 32] &= ~(1 << (val % 32)); > + irq_update = true; > + } This seems to ignore the nasty bit of the PLIC spec where a write to CLAIM is ignored if the interrupt is masked. M. -- Without deviation from the norm, progress is not possible.