From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 954DDC433F5 for ; Tue, 23 Nov 2021 10:03:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235159AbhKWKGw (ORCPT ); Tue, 23 Nov 2021 05:06:52 -0500 Received: from mail.kernel.org ([198.145.29.99]:38492 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231838AbhKWKGt (ORCPT ); Tue, 23 Nov 2021 05:06:49 -0500 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2CEB46102A; Tue, 23 Nov 2021 10:03:42 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mpSeJ-007FJe-Lw; Tue, 23 Nov 2021 10:03:39 +0000 Date: Tue, 23 Nov 2021 10:03:39 +0000 Message-ID: <87o86bchok.wl-maz@kernel.org> From: Marc Zyngier To: Reiji Watanabe Cc: kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata Subject: Re: [RFC PATCH v3 02/29] KVM: arm64: Save ID registers' sanitized value per vCPU In-Reply-To: References: <20211117064359.2362060-1-reijiw@google.com> <20211117064359.2362060-3-reijiw@google.com> <87lf1hsn11.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: reijiw@google.com, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, pbonzini@redhat.com, will@kernel.org, drjones@redhat.com, liangpeng10@huawei.com, pshier@google.com, ricarkol@google.com, oupton@google.com, jingzhangos@google.com, rananta@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Tue, 23 Nov 2021 04:39:27 +0000, Reiji Watanabe wrote: > > On Sun, Nov 21, 2021 at 4:37 AM Marc Zyngier wrote: > > > > On Wed, 17 Nov 2021 06:43:32 +0000, > > Reiji Watanabe wrote: > > > > > > Extend sys_regs[] of kvm_cpu_context for ID registers and save ID > > > registers' sanitized value in the array for the vCPU at the first > > > vCPU reset. Use the saved ones when ID registers are read by > > > userspace (via KVM_GET_ONE_REG) or the guest. > > > > > > Signed-off-by: Reiji Watanabe > > > --- > > > arch/arm64/include/asm/kvm_host.h | 10 +++++++ > > > arch/arm64/kvm/sys_regs.c | 43 +++++++++++++++++++------------ > > > 2 files changed, 37 insertions(+), 16 deletions(-) > > > > > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h > > > index edbe2cb21947..72db73c79403 100644 > > > --- a/arch/arm64/include/asm/kvm_host.h > > > +++ b/arch/arm64/include/asm/kvm_host.h > > > @@ -146,6 +146,14 @@ struct kvm_vcpu_fault_info { > > > u64 disr_el1; /* Deferred [SError] Status Register */ > > > }; > > > > > > +/* > > > + * (Op0, Op1, CRn, CRm, Op2) of ID registers is (3, 0, 0, crm, op2), > > > + * where 0<=crm<8, 0<=op2<8. > > > + */ > > > +#define KVM_ARM_ID_REG_MAX_NUM 64 > > > +#define IDREG_IDX(id) ((sys_reg_CRm(id) << 3) | sys_reg_Op2(id)) > > > +#define IDREG_SYS_IDX(id) (ID_REG_BASE + IDREG_IDX(id)) > > > + > > > enum vcpu_sysreg { > > > __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ > > > MPIDR_EL1, /* MultiProcessor Affinity Register */ > > > @@ -210,6 +218,8 @@ enum vcpu_sysreg { > > > CNTP_CVAL_EL0, > > > CNTP_CTL_EL0, > > > > > > + ID_REG_BASE, > > > + ID_REG_END = ID_REG_BASE + KVM_ARM_ID_REG_MAX_NUM - 1, > > > > It is rather unclear to me why we want these registers to be > > replicated on a per-CPU basis. Yes, this fits the architecture, but > > that's also a total waste of memory if you have more than a single > > CPU, because we make a point in only exposing homogeneous properties > > to the VM (I don't think anyone intends to support vcpu asymmetry in a > > VM, and 64 registers per vcpu is not an insignificant memory usage). > > > > If there are no reasons for this to be per-CPU, please move it to be > > global to the VM. This also mean that once a vcpu has reset, it > > shouldn't be possible to affect the registers. This shouldn't affect > > the userspace API though. > > > Currently, userspace can configure different CPU features for each vCPU > with KVM_ARM_VCPU_INIT, which indirectly affect ID registers. > I'm not sure if anyone actually does that though. But the way the ID regs are affected is always global AFAICT. For example, if you instantiate a PMU, you do so on all vcpus, even of the architecture allows you to build something completely asymmetric. > Since I personally thought having ID registers per vCPU more naturally > fits the behavior of KVM_ARM_VCPU_INIT and makes more straightforward > behavior of KVM_SET_ONE_REG, I chose that. I agree that this is the logical approach from an architectural PoV. > (That would be also better in terms of vCPUs scalability for live migration > considering a case where userspace tries to restore ID registers for > many vCPUs in parallel during live migration. Userspace could avoid that, > and there are ways for KVM to mitigate that though.) I think these are orthogonal things. We can expose a per-vcpu view, but there is no need to have per-vcpu storage and to allow asymmetric VMs. If I have anything to say about the future of KVM/arm64, it will be that I don't want to support this at all. > Having ID registers per-VM is of course feasible even while maintaining > the current behavior of KVM_ARM_VCPU_INIT though. Exactly. per-VM storage, and per-vcpu visibility. It will prevent all sort of odd behaviours. M. -- Without deviation from the norm, progress is not possible.