From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBEE1C25B0C for ; Wed, 10 Aug 2022 09:28:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232090AbiHJJ1m (ORCPT ); Wed, 10 Aug 2022 05:27:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232063AbiHJJ1c (ORCPT ); Wed, 10 Aug 2022 05:27:32 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 651B56B648 for ; Wed, 10 Aug 2022 02:27:31 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 02C7A61077 for ; Wed, 10 Aug 2022 09:27:31 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5F774C433D7; Wed, 10 Aug 2022 09:27:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660123650; bh=9HTAH6K930gonadYZGZRDhPFM/cwQux5OEOOD0cVV3k=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=GsWZMfbqajN2Qm26gCzwZFgNPUk5pdYw4q1d7Ha8Ia9cM/AK3aG+ypXl2jvsIsHO1 t8CROwILoC3De8jsab1LPuYB5DNMz/prTg//R8iMUh0yChDajx2HCXzCMJHWT7TdYs LJZlUzrrUyXmL0cQoKRKMObzq8fXOjJvQb7WdqzbvQbky/XcrE2zJ0NjekeBLGPLYN aUhm2+eFMNoNXiVH0FzhKakcIOf/0jcwrgr3+A7YmLumbDAn2gyBoBPv9lndPhBUMX 2kQDn7IuwqkWN4P1qboD5oVP/J+W2aftBELYHWaFJd1yFJeRgqNRxw3cDbCbu3zHn1 qjeBKPkYkKKBg== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1oLhzs-00262D-1S; Wed, 10 Aug 2022 10:27:28 +0100 Date: Wed, 10 Aug 2022 10:27:27 +0100 Message-ID: <87tu6kv474.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, James Morse , Suzuki K Poulose , Alexandru Elisei , Ricardo Koller , kernel-team@android.com Subject: Re: [PATCH 7/9] KVM: arm64: PMU: Allow ID_AA64DFR0_EL1.PMUver to be set from userspace In-Reply-To: References: <20220805135813.2102034-1-maz@kernel.org> <20220805135813.2102034-8-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, alexandru.elisei@arm.com, ricarkol@google.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Wed, 10 Aug 2022 08:08:06 +0100, Oliver Upton wrote: > > Hi Marc, > > On Fri, Aug 05, 2022 at 02:58:11PM +0100, Marc Zyngier wrote: > > Allow userspace to write ID_AA64DFR0_EL1, on the condition that only > > the PMUver field can be altered and be at most the one that was > > initially computed for the guest. > > As DFR0_EL1 is exposed to userspace, isn't a ->set_user() hook required > for it as well? Hmm. Yes, absolutely. Which is really annoying. It also pushed me to have a look at what PMUv3p5 means for AArch32, and it is utter nonsense... Here's what the spec says about PMEVCNTR: If FEAT_PMUv3p5 is implemented, the event counter is 64 bits and only the least-significant part of the event counter is accessible in AArch32 state: - Reads from PMEVCNTR return bits [31:0] of the counter. - Writes to PMEVCNTR update bits [31:0] and leave bits [63:32] unchanged. - There is no means to access bits [63:32] directly from AArch32 state But PMCR.LP does exist! You just can't make any reasonable use of it. Yet another reason to want AArch32 dead. > > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kvm/sys_regs.c | 35 ++++++++++++++++++++++++++++++++++- > > 1 file changed, 34 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > > index 55451f49017c..c0595f31dab8 100644 > > --- a/arch/arm64/kvm/sys_regs.c > > +++ b/arch/arm64/kvm/sys_regs.c > > @@ -1236,6 +1236,38 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, > > return 0; > > } > > > > +static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, > > + const struct sys_reg_desc *rd, > > + u64 val) > > +{ > > + u8 pmuver, host_pmuver; > > + > > + host_pmuver = kvm_arm_pmu_get_host_pmuver(); > > + > > + /* > > + * Allow AA64DFR0_EL1.PMUver to be set from userspace as long > > + * as it doesn't promise more than what the HW gives us. We > > + * don't allow an IMPDEF PMU though. > > + */ > > + pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_PMUVER), val); > > + if (pmuver == ID_AA64DFR0_PMUVER_IMP_DEF || pmuver > host_pmuver) > > + return -EINVAL; > > + > > + /* We already have a PMU, don't try to disable it... */ > > + if (kvm_vcpu_has_pmu(vcpu) && pmuver == 0) > > + return -EINVAL; > > + > > + /* We can only differ with PMUver, and anything else is an error */ > > + val ^= read_id_reg(vcpu, rd, false); > > + val &= ~(0xFUL << ID_AA64DFR0_PMUVER_SHIFT); > > nit: ~ARM64_FEATURE_MASK(ID_AA64DFR0_PMUVER) Good point. Thanks, M. -- Without deviation from the norm, progress is not possible.