From: Marc Zyngier <maz@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Megha Dey <megha.dey@intel.com>,
linux-kernel@vger.kernel.org, dave.jiang@intel.com,
ashok.raj@intel.com, kevin.tian@intel.com, dwmw@amazon.co.uk,
x86@kernel.org, tony.luck@intel.com, dan.j.williams@intel.com,
jgg@mellanox.com, kvm@vger.kernel.org,
iommu@lists.linux-foundation.org, alex.williamson@redhat.com,
bhelgaas@google.com, linux-pci@vger.kernel.org,
baolu.lu@linux.intel.com, ravi.v.shankar@intel.com
Subject: Re: [Patch V2 07/13] irqdomain/msi: Provide msi_alloc/free_store() callbacks
Date: Fri, 26 Mar 2021 10:14:30 +0000 [thread overview]
Message-ID: <87wntufchl.wl-maz@kernel.org> (raw)
In-Reply-To: <87lfabvzrz.fsf@nanos.tec.linutronix.de>
On Thu, 25 Mar 2021 18:44:48 +0000,
Thomas Gleixner <tglx@linutronix.de> wrote:
>
> On Thu, Mar 25 2021 at 17:08, Marc Zyngier wrote:
> > Megha Dey <megha.dey@intel.com> wrote:
> >> @@ -434,6 +434,12 @@ int __msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
> >> if (ret)
> >> return ret;
> >>
> >> + if (ops->msi_alloc_store) {
> >> + ret = ops->msi_alloc_store(domain, dev, nvec);
> >
> > What is supposed to happen if we get aliasing devices (similar to what
> > we have with devices behind a PCI bridge)?
> >
> > The ITS code goes through all kind of hoops to try and detect this
> > case when sizing the translation tables (in the .prepare callback),
> > and I have the feeling that sizing the message store is analogous.
>
> No. The message store itself is sized upfront by the underlying 'master'
> device. Each 'master' device has it's own irqdomain.
>
> This is the allocation for the subdevice and this is not part of PCI and
> therefore not subject to PCI aliasing.
Fair enough. If we are guaranteed that there is no aliasing, then this
point is moot.
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2021-03-26 10:15 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-26 20:11 [Patch V2 00/13] Introduce dev-msi and interrupt message store Megha Dey
2021-02-26 20:11 ` [Patch V2 01/13] x86/irq: Add DEV_MSI allocation type Megha Dey
2021-02-26 20:11 ` [Patch V2 02/13] x86/msi: Rename and rework pci_msi_prepare() to cover non-PCI MSI Megha Dey
2021-02-26 20:11 ` [Patch V2 03/13] platform-msi: Provide default irq_chip:: Ack Megha Dey
2021-02-26 20:11 ` [Patch V2 04/13] genirq/proc: Take buslock on affinity write Megha Dey
2021-02-26 20:11 ` [Patch V2 05/13] genirq/msi: Provide and use msi_domain_set_default_info_flags() Megha Dey
2021-02-26 20:11 ` [Patch V2 06/13] platform-msi: Add device MSI infrastructure Megha Dey
2021-02-26 20:11 ` [Patch V2 07/13] irqdomain/msi: Provide msi_alloc/free_store() callbacks Megha Dey
2021-03-25 17:08 ` Marc Zyngier
2021-03-25 18:44 ` Thomas Gleixner
2021-03-26 10:14 ` Marc Zyngier [this message]
2021-02-26 20:11 ` [Patch V2 08/13] genirq: Set auxiliary data for an interrupt Megha Dey
2021-03-25 17:23 ` Marc Zyngier
2021-03-25 18:59 ` Thomas Gleixner
2021-03-26 10:32 ` Marc Zyngier
2021-03-26 15:09 ` Thomas Gleixner
2021-02-26 20:11 ` [Patch V2 09/13] iommu/vt-d: Add DEV-MSI support Megha Dey
2021-02-26 20:11 ` [Patch V2 10/13] iommu: Add capability IOMMU_CAP_VIOMMU_HINT Megha Dey
2021-02-26 20:11 ` [Patch V2 11/13] platform-msi: Add platform check for subdevice irq domain Megha Dey
2021-02-26 20:11 ` [Patch V2 12/13] irqchip: Add IMS (Interrupt Message Store) driver Megha Dey
2021-03-25 17:43 ` Marc Zyngier
2021-03-25 19:07 ` Thomas Gleixner
2021-03-26 1:03 ` Dey, Megha
2021-02-26 20:11 ` [Patch V2 13/13] genirq/msi: Provide helpers to return Linux IRQ/dev_msi hw IRQ number Megha Dey
2021-03-25 17:53 ` Marc Zyngier
2021-03-26 1:02 ` Dey, Megha
2021-03-26 12:58 ` Marc Zyngier
2021-03-30 1:57 ` Dey, Megha
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