From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=BAYES_00,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06E0EC07E9B for ; Tue, 6 Jul 2021 14:52:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E5B6F613B2 for ; Tue, 6 Jul 2021 14:52:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232666AbhGFOzb convert rfc822-to-8bit (ORCPT ); Tue, 6 Jul 2021 10:55:31 -0400 Received: from mail.kernel.org ([198.145.29.99]:42312 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232655AbhGFOz2 (ORCPT ); Tue, 6 Jul 2021 10:55:28 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 90D40613B2; Tue, 6 Jul 2021 14:52:48 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1m0mRK-00BkmS-Ha; Tue, 06 Jul 2021 15:52:46 +0100 Date: Tue, 06 Jul 2021 15:52:46 +0100 Message-ID: <87y2aj7av5.wl-maz@kernel.org> From: Marc Zyngier To: Alexandre Chartre Cc: will@kernel.org, catalin.marinas@arm.com, alexandru.elisei@arm.com, james.morse@arm.com, suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, konrad.wilk@oracle.com Subject: Re: [PATCH] KVM: arm64: Disabling disabled PMU counters wastes a lot of time In-Reply-To: References: <20210628161925.401343-1-alexandre.chartre@oracle.com> <878s2tavks.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: alexandre.chartre@oracle.com, will@kernel.org, catalin.marinas@arm.com, alexandru.elisei@arm.com, james.morse@arm.com, suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, konrad.wilk@oracle.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Tue, 06 Jul 2021 14:50:35 +0100, Alexandre Chartre wrote: > > > Hi Marc, > > On 6/29/21 3:16 PM, Alexandre Chartre wrote: > > On 6/29/21 11:06 AM, Marc Zyngier wrote > > [...] > >> So the sysreg is the only thing we should consider, and I think we > >> should drop the useless masking. There is at least another instance of > >> this in the PMU code (kvm_pmu_overflow_status()), and apart from > >> kvm_pmu_vcpu_reset(), only the sysreg accessors should care about the > >> masking to sanitise accesses. > >> > >> What do you think? > >> > > > > I think you are right. PMCNTENSET_EL0 is already masked with kvm_pmu_valid_counter_mask() > > so there's effectively no need to mask it again when we use it. I will send an additional > > patch (on top of this one) to remove useless masking. Basically, changes would be: > > I had a closer look and we can't remove the mask. The access > functions (for pmcnten, pminten, pmovs), clear or set only the > specified valid counter bits. This means that bits other than the > valid counter bits never change in __vcpu_sys_reg(), and those bits > are not necessarily zero because the initial value is > 0x1de7ec7edbadc0deULL (set by reset_unknown()). That's a bug that should be fixed on its own. Bits that are RAZ/WI in the architecture shouldn't be kept in the shadow registers the first place. I'll have a look. > So I will resubmit initial patch, with just the commit message > changes. Please don't. I'm not papering over this kind of bug. Thanks, M. -- Without deviation from the norm, progress is not possible.