From: Conor Dooley <conor.dooley@microchip.com>
To: Nathan Chancellor <nathan@kernel.org>, Andy Chiu <andy.chiu@sifive.com>
Cc: Andy Chiu <andy.chiu@sifive.com>,
<linux-riscv@lists.infradead.org>, <palmer@dabbelt.com>,
<anup@brainfault.org>, <atishp@atishpatra.org>,
<kvm-riscv@lists.infradead.org>, <kvm@vger.kernel.org>,
<vineetg@rivosinc.com>, <greentime.hu@sifive.com>,
<guoren@linux.alibaba.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Nick Desaulniers <ndesaulniers@google.com>,
Tom Rix <trix@redhat.com>
Subject: Re: [PATCH -next v15 19/19] riscv: Enable Vector code to be built
Date: Mon, 20 Mar 2023 13:47:48 +0000 [thread overview]
Message-ID: <8dba167d-5b68-472c-992f-05b80404f557@spud> (raw)
In-Reply-To: <20230317154658.GA1122384@dev-arch.thelio-3990X>
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On Fri, Mar 17, 2023 at 08:46:58AM -0700, Nathan Chancellor wrote:
> On Fri, Mar 17, 2023 at 11:35:38AM +0000, Andy Chiu wrote:
> > From: Guo Ren <guoren@linux.alibaba.com>
> >
> > This patch adds a config which enables vector feature from the kernel
> > space.
> >
> > Support for RISC_V_ISA_V is limited to GNU-assembler for now, as LLVM
> > has not acquired the functionality to selectively change the arch option
> > in assembly code. This is still under review at
> > https://reviews.llvm.org/D123515
> >
> > Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> > Co-developed-by: Greentime Hu <greentime.hu@sifive.com>
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > Suggested-by: Vineet Gupta <vineetg@rivosinc.com>
> > Suggested-by: Atish Patra <atishp@atishpatra.org>
> > Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
> > Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> > ---
> > arch/riscv/Kconfig | 20 ++++++++++++++++++++
> > arch/riscv/Makefile | 6 +++++-
> > 2 files changed, 25 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index c736dc8e2593..bf9aba2f2811 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -436,6 +436,26 @@ config RISCV_ISA_SVPBMT
> >
> > If you don't know what to do here, say Y.
> >
> > +config TOOLCHAIN_HAS_V
> > + bool
> > + default y
> > + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64iv)
> > + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32iv)
> > + depends on LLD_VERSION >= 140000 || LD_VERSION >= 23800
> > + depends on AS_IS_GNU
>
> Consider hoisting this 'depends on AS_IS_GNU' into its own configuration
> option, as the same dependency is present in CONFIG_TOOLCHAIN_HAS_ZBB
> for the exact same reason, with no comment as to why. By having a shared
> dependency configuration option, we can easily update it when that
> change is merged into LLVM proper and gain access to the current and
> future options that depend on it. I imagine something like:
>
> config AS_HAS_OPTION_ARCH
> bool
> default y
> # https://reviews.llvm.org/D123515
> depends on AS_IS_GNU
>
> config TOOLCHAIN_HAS_ZBB
> bool
> default y
> depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbb)
> depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbb)
> depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
> depends on AS_HAS_OPTION_ARCH
>
> config TOOLCHAIN_HAS_V
> bool
> default y
> depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64iv)
> depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32iv)
> depends on LLD_VERSION >= 140000 || LD_VERSION >= 23800
> depends on AS_HAS_OPTION_ARCH
>
> It would be nice if it was a hard error for LLVM like GCC so that we
> could just dynamically check support via as-instr but a version check is
> not the end of the world when we know the versions.
Yah, this is a good idea Nathan, since we may end up having to do the
same thing for a decent number of extensions going forward. Could you
please implement this Andy?
> > +config RISCV_ISA_V
> > + bool "VECTOR extension support"
> > + depends on TOOLCHAIN_HAS_V
> > + depends on FPU
> > + select DYNAMIC_SIGFRAME
> > + default y
> > + help
> > + Say N here if you want to disable all vector related procedure
> > + in the kernel.
> > +
> > + If you don't know what to do here, say Y.
> > +
> > config TOOLCHAIN_HAS_ZBB
> > bool
> > default y
> > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> > index 6203c3378922..84a50cfaedf9 100644
> > --- a/arch/riscv/Makefile
> > +++ b/arch/riscv/Makefile
> > @@ -56,6 +56,7 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
> > riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
> > riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
> > riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
> > +riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v
> >
> > # Newer binutils versions default to ISA spec version 20191213 which moves some
> > # instructions from the I extension to the Zicsr and Zifencei extensions.
> > @@ -65,7 +66,10 @@ riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
> > # Check if the toolchain supports Zihintpause extension
> > riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause
> >
> > -KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
> > +# Remove F,D,V from isa string for all. Keep extensions between "fd" and "v" by
> > +# keep non-v and multi-letter extensions out with the filter ([^v_]*)
> > +KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\2/')
^
Is the extra space here intentional?
It's a shame that this had to become so complicated, but thanks for
adding a comment so that the rationale behind the complexity can be
understood.
Perhaps there's a case to be made for removing fd & v separately to make
things more understandable, but I think the removal of v is going to
look complex in both cases.
I'm happy with doing it like this now, but if, in the future, we need to
account for possibly having q too, I might advocate for the split rather
than adding more complexity.
With Nathan's suggestion of AS_HAS_OPTION_ARCH:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
> > +
> > KBUILD_AFLAGS += -march=$(riscv-march-y)
> >
> > KBUILD_CFLAGS += -mno-save-restore
> > --
> > 2.17.1
> >
>
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next prev parent reply other threads:[~2023-03-20 13:48 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-17 11:35 [PATCH -next v15 00/19] riscv: Add vector ISA support Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 01/19] riscv: Rename __switch_to_aux() -> fpu Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 02/19] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 03/19] riscv: Add new csr defines related to vector extension Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 04/19] riscv: Clear vector regfile on bootup Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 05/19] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 06/19] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 07/19] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu
2023-03-20 13:02 ` Conor Dooley
2023-03-17 11:35 ` [PATCH -next v15 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-03-20 13:05 ` Conor Dooley
2023-03-20 14:46 ` Andy Chiu
2023-03-20 14:54 ` Conor Dooley
2023-03-22 1:54 ` Guo Ren
2023-03-23 10:21 ` Björn Töpel
2023-03-17 11:35 ` [PATCH -next v15 09/19] riscv: Add task switch support for vector Andy Chiu
2023-03-20 13:07 ` Conor Dooley
2023-03-23 10:23 ` Björn Töpel
2023-03-17 11:35 ` [PATCH -next v15 10/19] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-03-20 13:27 ` Conor Dooley
2023-03-23 10:29 ` Björn Töpel
2023-03-17 11:35 ` [PATCH -next v15 11/19] riscv: Add ptrace vector support Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 12/19] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 13/19] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-03-20 13:36 ` Conor Dooley
2023-03-23 7:50 ` Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 14/19] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-03-23 10:36 ` Björn Töpel
2023-03-23 14:39 ` Guo Ren
2023-03-17 11:35 ` [PATCH -next v15 15/19] riscv: signal: validate altstack to reflect Vector Andy Chiu
2023-03-20 13:40 ` Conor Dooley
2023-03-17 11:35 ` [PATCH -next v15 16/19] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 17/19] riscv: kvm: Add V extension to KVM ISA Andy Chiu
2023-03-17 11:54 ` Anup Patel
2023-03-17 11:35 ` [PATCH -next v15 18/19] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-03-17 12:02 ` Anup Patel
2023-03-17 11:35 ` [PATCH -next v15 19/19] riscv: Enable Vector code to be built Andy Chiu
2023-03-17 15:46 ` Nathan Chancellor
2023-03-20 13:47 ` Conor Dooley [this message]
2023-03-23 10:44 ` [PATCH -next v15 00/19] riscv: Add vector ISA support Björn Töpel
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