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([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.gmail.com with ESMTPSA id f77sm3622230wmf.42.2021.01.05.03.47.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 05 Jan 2021 03:47:24 -0800 (PST) Subject: Re: [PATCH 1/2] Enumerate AVX Vector Neural Network instructions To: Yang Zhong , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, bp@alien8.de Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, tony.luck@intel.com, seanjc@google.com, vkuznets@redhat.com, wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org, kyung.min.park@intel.com, x86@kernel.org References: <20210105004909.42000-1-yang.zhong@intel.com> <20210105004909.42000-2-yang.zhong@intel.com> From: Paolo Bonzini Message-ID: <8fa46290-28d8-5f61-1ce4-8e83bf911106@redhat.com> Date: Tue, 5 Jan 2021 12:47:23 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.5.0 MIME-Version: 1.0 In-Reply-To: <20210105004909.42000-2-yang.zhong@intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On 05/01/21 01:49, Yang Zhong wrote: > From: Kyung Min Park > > Add AVX version of the Vector Neural Network (VNNI) Instructions. > > A processor supports AVX VNNI instructions if CPUID.0x07.0x1:EAX[4] is > present. The following instructions are available when this feature is > present. > 1. VPDPBUS: Multiply and Add Unsigned and Signed Bytes > 2. VPDPBUSDS: Multiply and Add Unsigned and Signed Bytes with Saturation > 3. VPDPWSSD: Multiply and Add Signed Word Integers > 4. VPDPWSSDS: Multiply and Add Signed Integers with Saturation > > The only in-kernel usage of this is kvm passthrough. The CPU feature > flag is shown as "avx_vnni" in /proc/cpuinfo. > > This instruction is currently documented in the latest "extensions" > manual (ISE). It will appear in the "main" manual (SDM) in the future. > > Signed-off-by: Kyung Min Park > Signed-off-by: Yang Zhong > Reviewed-by: Tony Luck > --- > arch/x86/include/asm/cpufeatures.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index f5ef2d5b9231..d10d9962bd9b 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -293,6 +293,7 @@ > #define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */ > > /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ > +#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ > #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ > > /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ > Boris, is it possible to have a topic branch for this patch?