From: Nadav Amit <nadav.amit@gmail.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: Thomas Huth <thuth@redhat.com>, Like Xu <like.xu@linux.intel.com>,
Sean Christopherson <sean.j.christopherson@intel.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [kvm-unit-tests PATCH] x86: pmu: Test full-width counter writes support
Date: Fri, 19 Jun 2020 12:46:12 -0700 [thread overview]
Message-ID: <A2E707BF-BF31-4B96-9181-881B5E496938@gmail.com> (raw)
In-Reply-To: <1272fbd7-3ff1-5eac-e9e2-78b824fbc4e0@redhat.com>
> On Jun 16, 2020, at 5:28 AM, Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> On 16/06/20 12:49, Thomas Huth wrote:
>> On 29/05/2020 09.43, Like Xu wrote:
>>> When the full-width writes capability is set, use the alternative MSR
>>> range to write larger sign counter values (up to GP counter width).
>>>
>>> Signed-off-by: Like Xu <like.xu@linux.intel.com>
>>> ---
>>> lib/x86/msr.h | 1 +
>>> x86/pmu.c | 125 ++++++++++++++++++++++++++++++++++++++++----------
>>> 2 files changed, 102 insertions(+), 24 deletions(-)
>> [...]
>>> @@ -452,6 +468,66 @@ static void check_running_counter_wrmsr(void)
>>> report_prefix_pop();
>>> }
>>>
>>> +static void check_counters(void)
>>> +{
>>> + check_gp_counters();
>>> + check_fixed_counters();
>>> + check_rdpmc();
>>> + check_counters_many();
>>> + check_counter_overflow();
>>> + check_gp_counter_cmask();
>>> + check_running_counter_wrmsr();
>>> +}
>>> +
>>> +static void do_unsupported_width_counter_write(void *index)
>>> +{
>>> + wrmsr(MSR_IA32_PMC0 + *((int *) index), 0xffffff0123456789ull);
>>> +}
>>> +
>>> +static void check_gp_counters_write_width(void)
>>> +{
>>> + u64 val_64 = 0xffffff0123456789ull;
>>> + u64 val_32 = val_64 & ((1ul << 32) - 1);
>> Hi,
>>
>> this broke compilation on 32-bit hosts:
>>
>> https://travis-ci.com/github/huth/kvm-unit-tests/jobs/349654654#L710
>>
>> Fix should be easy, I guess - either use 1ull or specify the mask
>> 0xffffffff directly.
>
> Or
>
> u64 val_32 = (u64)(u32) val_64;
>
> I'll send a patch.
I missed this correspondence, but while running the tests on 32-bit I
encountered two additional cases of wrong masks that caused failures.
I have sent a separate patch for your consideration.
next prev parent reply other threads:[~2020-06-19 19:46 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-29 7:43 [PATCH RESEND] Enable full width counting for KVM: x86/pmu Like Xu
2020-05-29 7:43 ` [PATCH RESEND v4 1/2] KVM: x86/pmu: Tweak kvm_pmu_get_msr to pass 'struct msr_data' in Like Xu
2020-05-29 7:43 ` [PATCH RESEND v4 2/2] KVM: x86/pmu: Support full width counting Like Xu
2020-05-29 7:43 ` [kvm-unit-tests PATCH] x86: pmu: Test full-width counter writes support Like Xu
2020-06-16 10:49 ` Thomas Huth
2020-06-16 12:28 ` Paolo Bonzini
2020-06-19 19:46 ` Nadav Amit [this message]
2021-05-11 21:27 ` Jim Mattson
2021-05-12 6:33 ` Like Xu
2022-01-08 0:06 ` Jim Mattson
2022-01-10 6:34 ` Like Xu
2022-03-11 16:36 ` Thomas Huth
2020-05-29 7:43 ` [Qemu-devel PATCH] target/i386: define a new MSR based feature word - FEAT_PERF_CAPABILITIES Like Xu
2020-05-29 10:23 ` Paolo Bonzini
2020-05-29 8:47 ` [PATCH RESEND] Enable full width counting for KVM: x86/pmu Paolo Bonzini
2020-05-29 8:52 ` Xu, Like
-- strict thread matches above, loose matches on Subject: below --
2020-05-08 8:32 [PATCH v3] KVM: x86/pmu: Support full width counting Like Xu
2020-05-08 8:32 ` [kvm-unit-tests PATCH] x86: pmu: Test full-width counter writes support Like Xu
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