From: Anup Patel <anup@brainfault.org>
To: Atish Patra <atishp@rivosinc.com>
Cc: "linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>, Atish Patra <atish.patra@wdc.com>,
Anup Patel <anup.patel@wdc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Heinrich Schuchardt <xypron.glpk@gmx.de>,
Kefeng Wang <wangkefeng.wang@huawei.com>,
kvm-riscv@lists.infradead.org, KVM General <kvm@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>
Subject: Re: [PATCH v5 4/5] RISC-V: KVM: Add v0.1 replacement SBI extensions defined in v02
Date: Tue, 23 Nov 2021 13:33:50 +0530 [thread overview]
Message-ID: <CAAhSdy2yZcNBXt00jqLKc2g+SeiytmefzTP=4OPO9f_bXtv8BA@mail.gmail.com> (raw)
In-Reply-To: <20211118083912.981995-5-atishp@rivosinc.com>
On Thu, Nov 18, 2021 at 2:10 PM Atish Patra <atishp@rivosinc.com> wrote:
>
> From: Atish Patra <atish.patra@wdc.com>
>
> The SBI v0.2 contains some of the improved versions of required v0.1
> extensions such as remote fence, timer and IPI.
>
> This patch implements those extensions.
>
> Reviewed-by: Anup Patel <anup.patel@wdc.com>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
I have queued this for 5.17
Thanks,
Anup
> ---
> arch/riscv/kvm/Makefile | 1 +
> arch/riscv/kvm/vcpu_sbi.c | 7 ++
> arch/riscv/kvm/vcpu_sbi_replace.c | 133 ++++++++++++++++++++++++++++++
> 3 files changed, 141 insertions(+)
> create mode 100644 arch/riscv/kvm/vcpu_sbi_replace.c
>
> diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile
> index 84c02922a329..4757ae158bf3 100644
> --- a/arch/riscv/kvm/Makefile
> +++ b/arch/riscv/kvm/Makefile
> @@ -25,4 +25,5 @@ kvm-y += vcpu_switch.o
> kvm-y += vcpu_sbi.o
> kvm-$(CONFIG_RISCV_SBI_V01) += vcpu_sbi_v01.o
> kvm-y += vcpu_sbi_base.o
> +kvm-y += vcpu_sbi_replace.o
> kvm-y += vcpu_timer.o
> diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c
> index 915a044a0b4f..cf284e080f3e 100644
> --- a/arch/riscv/kvm/vcpu_sbi.c
> +++ b/arch/riscv/kvm/vcpu_sbi.c
> @@ -40,9 +40,16 @@ static const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01 = {
> };
> #endif
> extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_base;
> +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_time;
> +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_ipi;
> +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence;
> +
> static const struct kvm_vcpu_sbi_extension *sbi_ext[] = {
> &vcpu_sbi_ext_v01,
> &vcpu_sbi_ext_base,
> + &vcpu_sbi_ext_time,
> + &vcpu_sbi_ext_ipi,
> + &vcpu_sbi_ext_rfence,
> };
>
> void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run)
> diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_replace.c
> new file mode 100644
> index 000000000000..67a64db1efc9
> --- /dev/null
> +++ b/arch/riscv/kvm/vcpu_sbi_replace.c
> @@ -0,0 +1,133 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021 Western Digital Corporation or its affiliates.
> + *
> + * Authors:
> + * Atish Patra <atish.patra@wdc.com>
> + */
> +
> +#include <linux/errno.h>
> +#include <linux/err.h>
> +#include <linux/kvm_host.h>
> +#include <asm/csr.h>
> +#include <asm/sbi.h>
> +#include <asm/kvm_vcpu_timer.h>
> +#include <asm/kvm_vcpu_sbi.h>
> +
> +static int kvm_sbi_ext_time_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
> + unsigned long *out_val,
> + struct kvm_cpu_trap *utrap, bool *exit)
> +{
> + int ret = 0;
> + struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
> + u64 next_cycle;
> +
> + if (cp->a6 != SBI_EXT_TIME_SET_TIMER)
> + return -EINVAL;
> +
> +#if __riscv_xlen == 32
> + next_cycle = ((u64)cp->a1 << 32) | (u64)cp->a0;
> +#else
> + next_cycle = (u64)cp->a0;
> +#endif
> + kvm_riscv_vcpu_timer_next_event(vcpu, next_cycle);
> +
> + return ret;
> +}
> +
> +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_time = {
> + .extid_start = SBI_EXT_TIME,
> + .extid_end = SBI_EXT_TIME,
> + .handler = kvm_sbi_ext_time_handler,
> +};
> +
> +static int kvm_sbi_ext_ipi_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
> + unsigned long *out_val,
> + struct kvm_cpu_trap *utrap, bool *exit)
> +{
> + int i, ret = 0;
> + struct kvm_vcpu *tmp;
> + struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
> + unsigned long hmask = cp->a0;
> + unsigned long hbase = cp->a1;
> +
> + if (cp->a6 != SBI_EXT_IPI_SEND_IPI)
> + return -EINVAL;
> +
> + kvm_for_each_vcpu(i, tmp, vcpu->kvm) {
> + if (hbase != -1UL) {
> + if (tmp->vcpu_id < hbase)
> + continue;
> + if (!(hmask & (1UL << (tmp->vcpu_id - hbase))))
> + continue;
> + }
> + ret = kvm_riscv_vcpu_set_interrupt(tmp, IRQ_VS_SOFT);
> + if (ret < 0)
> + break;
> + }
> +
> + return ret;
> +}
> +
> +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_ipi = {
> + .extid_start = SBI_EXT_IPI,
> + .extid_end = SBI_EXT_IPI,
> + .handler = kvm_sbi_ext_ipi_handler,
> +};
> +
> +static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
> + unsigned long *out_val,
> + struct kvm_cpu_trap *utrap, bool *exit)
> +{
> + int i, ret = 0;
> + struct cpumask cm, hm;
> + struct kvm_vcpu *tmp;
> + struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
> + unsigned long hmask = cp->a0;
> + unsigned long hbase = cp->a1;
> + unsigned long funcid = cp->a6;
> +
> + cpumask_clear(&cm);
> + cpumask_clear(&hm);
> + kvm_for_each_vcpu(i, tmp, vcpu->kvm) {
> + if (hbase != -1UL) {
> + if (tmp->vcpu_id < hbase)
> + continue;
> + if (!(hmask & (1UL << (tmp->vcpu_id - hbase))))
> + continue;
> + }
> + if (tmp->cpu < 0)
> + continue;
> + cpumask_set_cpu(tmp->cpu, &cm);
> + }
> +
> + riscv_cpuid_to_hartid_mask(&cm, &hm);
> +
> + switch (funcid) {
> + case SBI_EXT_RFENCE_REMOTE_FENCE_I:
> + ret = sbi_remote_fence_i(cpumask_bits(&hm));
> + break;
> + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA:
> + ret = sbi_remote_hfence_vvma(cpumask_bits(&hm), cp->a2, cp->a3);
> + break;
> + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID:
> + ret = sbi_remote_hfence_vvma_asid(cpumask_bits(&hm), cp->a2,
> + cp->a3, cp->a4);
> + break;
> + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA:
> + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID:
> + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA:
> + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID:
> + /* TODO: implement for nested hypervisor case */
> + default:
> + ret = -EOPNOTSUPP;
> + }
> +
> + return ret;
> +}
> +
> +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence = {
> + .extid_start = SBI_EXT_RFENCE,
> + .extid_end = SBI_EXT_RFENCE,
> + .handler = kvm_sbi_ext_rfence_handler,
> +};
> --
> 2.33.1
>
>
> --
> kvm-riscv mailing list
> kvm-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/kvm-riscv
next prev parent reply other threads:[~2021-11-23 8:04 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-18 8:39 [PATCH v5 0/5] Add SBI v0.2 support for KVM Atish Patra
2021-11-18 8:39 ` [PATCH v5 1/5] RISC-V: KVM: Mark the existing SBI implementation as v01 Atish Patra
2021-11-23 8:02 ` Anup Patel
2022-01-04 13:19 ` Heiko Stübner
2022-01-04 13:27 ` Heiko Stübner
2022-01-04 13:59 ` Anup Patel
2021-11-18 8:39 ` [PATCH v5 2/5] RISC-V: KVM: Reorganize SBI code by moving SBI v0.1 to its own file Atish Patra
2021-11-23 8:02 ` Anup Patel
2021-11-18 8:39 ` [PATCH v5 3/5] RISC-V: KVM: Add SBI v0.2 base extension Atish Patra
2021-11-23 8:03 ` Anup Patel
2021-11-18 8:39 ` [PATCH v5 4/5] RISC-V: KVM: Add v0.1 replacement SBI extensions defined in v02 Atish Patra
2021-11-23 8:03 ` Anup Patel [this message]
2021-11-18 8:39 ` [PATCH v5 5/5] RISC-V: KVM: Add SBI HSM extension in KVM Atish Patra
2021-11-23 8:06 ` Anup Patel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAAhSdy2yZcNBXt00jqLKc2g+SeiytmefzTP=4OPO9f_bXtv8BA@mail.gmail.com' \
--to=anup@brainfault.org \
--cc=anup.patel@wdc.com \
--cc=aou@eecs.berkeley.edu \
--cc=atish.patra@wdc.com \
--cc=atishp@rivosinc.com \
--cc=kvm-riscv@lists.infradead.org \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=wangkefeng.wang@huawei.com \
--cc=xypron.glpk@gmx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).