From: Alistair Francis <alistair23@gmail.com>
To: Yifei Jiang <jiangyifei@huawei.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
kvm-riscv@lists.infradead.org,
"open list:Overall" <kvm@vger.kernel.org>,
libvir-list@redhat.com, Anup Patel <anup@brainfault.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
fanliang@huawei.com, "Wubin (H)" <wu.wubin@huawei.com>,
wanghaibin.wang@huawei.com, wanbo13@huawei.com,
Mingwang Li <limingwang@huawei.com>,
Anup Patel <anup.patel@wdc.com>
Subject: Re: [PATCH v4 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
Date: Mon, 10 Jan 2022 16:52:25 +1000 [thread overview]
Message-ID: <CAKmqyKNb4eDQVm4tMz1VJk006Y=X7tpuG8dAQ1Uuj02mHMMbKg@mail.gmail.com> (raw)
In-Reply-To: <20220110013831.1594-11-jiangyifei@huawei.com>
On Mon, Jan 10, 2022 at 11:54 AM Yifei Jiang via <qemu-devel@nongnu.org> wrote:
>
> Add kvm_riscv_get/put_regs_timer to synchronize virtual time context
> from KVM.
>
> To set register of RISCV_TIMER_REG(state) will occur a error from KVM
> on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter
> that adaping in QEMU.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Mingwang Li <limingwang@huawei.com>
> Reviewed-by: Anup Patel <anup.patel@wdc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 7 +++++
> target/riscv/kvm.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 79 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 5f54fae7cc..9eceded96c 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -261,6 +261,13 @@ struct CPURISCVState {
>
> hwaddr kernel_addr;
> hwaddr fdt_addr;
> +
> + /* kvm timer */
> + bool kvm_timer_dirty;
> + uint64_t kvm_timer_time;
> + uint64_t kvm_timer_compare;
> + uint64_t kvm_timer_state;
> + uint64_t kvm_timer_frequency;
> };
>
> OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index ded2a8c29d..b1f1d55f29 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -40,6 +40,7 @@
> #include "kvm_riscv.h"
> #include "sbi_ecall_interface.h"
> #include "chardev/char-fe.h"
> +#include "migration/migration.h"
>
> static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, uint64_t idx)
> {
> @@ -64,6 +65,9 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, uint64_t idx
> #define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
> KVM_REG_RISCV_CSR_REG(name))
>
> +#define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \
> + KVM_REG_RISCV_TIMER_REG(name))
> +
> #define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx)
>
> #define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
> @@ -84,6 +88,22 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, uint64_t idx
> } \
> } while(0)
>
> +#define KVM_RISCV_GET_TIMER(cs, env, name, reg) \
> + do { \
> + int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \
> + if (ret) { \
> + abort(); \
> + } \
> + } while(0)
> +
> +#define KVM_RISCV_SET_TIMER(cs, env, name, reg) \
> + do { \
> + int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, time), ®); \
> + if (ret) { \
> + abort(); \
> + } \
> + } while (0)
> +
> static int kvm_riscv_get_regs_core(CPUState *cs)
> {
> int ret = 0;
> @@ -235,6 +255,58 @@ static int kvm_riscv_put_regs_fp(CPUState *cs)
> return ret;
> }
>
> +static void kvm_riscv_get_regs_timer(CPUState *cs)
> +{
> + CPURISCVState *env = &RISCV_CPU(cs)->env;
> +
> + if (env->kvm_timer_dirty) {
> + return;
> + }
> +
> + KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time);
> + KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare);
> + KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state);
> + KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency);
> +
> + env->kvm_timer_dirty = true;
> +}
> +
> +static void kvm_riscv_put_regs_timer(CPUState *cs)
> +{
> + uint64_t reg;
> + CPURISCVState *env = &RISCV_CPU(cs)->env;
> +
> + if (!env->kvm_timer_dirty) {
> + return;
> + }
> +
> + KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time);
> + KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare);
> +
> + /*
> + * To set register of RISCV_TIMER_REG(state) will occur a error from KVM
> + * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it
> + * doesn't matter that adaping in QEMU now.
> + * TODO If KVM changes, adapt here.
> + */
> + if (env->kvm_timer_state) {
> + KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state);
> + }
> +
> + /*
> + * For now, migration will not work between Hosts with different timer
> + * frequency. Therefore, we should check whether they are the same here
> + * during the migration.
> + */
> + if (migration_is_running(migrate_get_current()->state)) {
> + KVM_RISCV_GET_TIMER(cs, env, frequency, reg);
> + if (reg != env->kvm_timer_frequency) {
> + error_report("Dst Hosts timer frequency != Src Hosts");
> + }
> + }
> +
> + env->kvm_timer_dirty = false;
> +}
>
> const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
> KVM_CAP_LAST_INFO
> --
> 2.19.1
>
>
next prev parent reply other threads:[~2022-01-10 6:52 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-10 1:38 [PATCH v4 00/12] Add riscv kvm accel support Yifei Jiang
2022-01-10 1:38 ` [PATCH v4 01/12] update-linux-headers: Add asm-riscv/kvm.h Yifei Jiang
2022-01-10 1:38 ` [PATCH v4 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
2022-01-10 23:09 ` Alistair Francis
2022-01-12 8:04 ` Jiangyifei
2022-01-10 1:38 ` [PATCH v4 03/12] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
2022-01-10 1:38 ` [PATCH v4 04/12] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
2022-01-10 1:38 ` [PATCH v4 05/12] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
2022-01-10 23:06 ` Alistair Francis
2022-01-12 8:01 ` Jiangyifei
2022-01-10 1:38 ` [PATCH v4 06/12] target/riscv: Support start kernel directly by KVM Yifei Jiang
2022-01-11 0:27 ` Alistair Francis
2022-01-12 8:07 ` Jiangyifei
2022-01-10 1:38 ` [PATCH v4 07/12] target/riscv: Support setting external interrupt " Yifei Jiang
2022-01-10 1:38 ` [PATCH v4 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang
2022-01-10 6:48 ` Alistair Francis
2022-01-10 1:38 ` [PATCH v4 09/12] target/riscv: Add host cpu type Yifei Jiang
2022-01-10 1:38 ` [PATCH v4 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang
2022-01-10 6:52 ` Alistair Francis [this message]
2022-01-10 1:38 ` [PATCH v4 11/12] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang
2022-01-10 1:38 ` [PATCH v4 12/12] target/riscv: Support virtual time context synchronization Yifei Jiang
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