From: Jim Mattson <jmattson@google.com>
To: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>, kvm list <kvm@vger.kernel.org>
Subject: Re: [PATCH 2/3 v4] KVM: nSVM: Check that MBZ bits in CR3 and CR4 are not set on vmrun of nested guests
Date: Wed, 8 Jul 2020 16:07:22 -0700 [thread overview]
Message-ID: <CALMp9eQRgRX4nnLHp52SY1emjjs7VO90pGKpV3Y0JJvf-bjNFQ@mail.gmail.com> (raw)
In-Reply-To: <ed07cbc2-991f-1f9e-9a4d-ef9b4294b373@oracle.com>
On Wed, Jul 8, 2020 at 3:51 PM Krish Sadhukhan
<krish.sadhukhan@oracle.com> wrote:
> Just curious about using LME instead of LMA. According to APM,
>
> " The processor behaves as a 32-bit x86 processor in all respects
> until long mode is activated, even if long mode is enabled. None of the
> new 64-bit data sizes, addressing, or system aspects available in long
> mode can be used until EFER.LMA=1."
>
>
> Is it possible that L1 sets LME, but not LMA, in L2's VMCS and this
> code will execute even if the processor is not in long-mode ?
No. EFER.LMA is not modifiable through software. It is always
"EFER.LME != 0 && CR0.PG != 0."
next prev parent reply other threads:[~2020-07-08 23:07 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-08 0:39 [PATCH 0/3 v4] KVM: nSVM: Check MBZ bits in CR3 and CR4 on vmrun of nested guests Krish Sadhukhan
2020-07-08 0:39 ` [PATCH 1/3 v4] KVM: x86: Create mask for guest CR4 reserved bits in kvm_update_cpuid() Krish Sadhukhan
2020-07-08 9:48 ` Paolo Bonzini
2020-07-08 0:39 ` [PATCH 2/3 v4] KVM: nSVM: Check that MBZ bits in CR3 and CR4 are not set on vmrun of nested guests Krish Sadhukhan
2020-07-08 10:03 ` Paolo Bonzini
2020-07-08 21:36 ` Krish Sadhukhan
2020-07-08 22:51 ` Krish Sadhukhan
2020-07-08 23:07 ` Jim Mattson [this message]
2020-07-09 9:36 ` Paolo Bonzini
2020-07-08 0:39 ` [PATCH 3/3 v4] kvm-unit-tests: nSVM: Test " Krish Sadhukhan
2020-07-08 11:07 ` Paolo Bonzini
2020-07-09 0:01 ` Krish Sadhukhan
2020-07-11 16:12 ` Nadav Amit
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