Re: [RFC][PATCH v2 1/1] KVM: nVMX: Don't leak L1 MMIO regions to L2

From: Jim Mattson <jmattson@google.com>
To: "Tian, Kevin" <kevin.tian@intel.com>
Cc: "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	Dan Cross <dcross@google.com>, Marc Orr <marcorr@google.com>,
	Peter Shier <pshier@google.com>
Subject: Re: [RFC][PATCH v2 1/1] KVM: nVMX: Don't leak L1 MMIO regions to L2
Date: Thu, 12 Sep 2019 09:25:01 -0700	[thread overview]
Message-ID: <CALMp9eRz7=nCQHHRUcgQ62majARu-+bTCyfuNd7mpn0vRAE-sA@mail.gmail.com> (raw)
In-Reply-To: <AADFC41AFE54684AB9EE6CBC0274A5D19D57154C@SHSMSX104.ccr.corp.intel.com>

On Thu, Sep 12, 2019 at 12:55 AM Tian, Kevin <kevin.tian@intel.com> wrote:
>
> > From: Tian, Kevin
> > Sent: Thursday, September 12, 2019 3:49 PM
> >
> > > From: Jim Mattson
> > > Sent: Tuesday, September 10, 2019 6:28 AM
> > >
> > > If the "virtualize APIC accesses" VM-execution control is set in the
> > > VMCS, the APIC virtualization hardware is triggered when a page walk
> > > in VMX non-root mode terminates at a PTE wherein the address of the 4k
> > > page frame matches the APIC-access address specified in the VMCS. On
> > > hardware, the APIC-access address may be any valid 4k-aligned physical
> > > address.
> > >
> > > KVM's nVMX implementation enforces the additional constraint that the
> > > APIC-access address specified in the vmcs12 must be backed by
> > > cacheable memory in L1. If not, L0 will simply clear the "virtualize
> > > APIC accesses" VM-execution control in the vmcs02.
> > >
> > > The problem with this approach is that the L1 guest has arranged the
> > > vmcs12 EPT tables--or shadow page tables, if the "enable EPT"
> > > VM-execution control is clear in the vmcs12--so that the L2 guest
> > > physical address(es)--or L2 guest linear address(es)--that reference
> > > the L2 APIC map to the APIC-access address specified in the
> > > vmcs12. Without the "virtualize APIC accesses" VM-execution control in
> > > the vmcs02, the APIC accesses in the L2 guest will directly access the
> > > APIC-access page in L1.
> > >
> > > When L0 has no mapping whatsoever for the APIC-access address in L1,
> > > the L2 VM just loses the intended APIC virtualization. However, when
> > > the L2 APIC-access address is mapped to an MMIO region in L1, the L2
> > > guest gets direct access to the L1 MMIO device. For example, if the
> > > APIC-access address specified in the vmcs12 is 0xfee00000, then L2
> > > gets direct access to L1's APIC.
> >
> > 'direct access to L1 APIC' is conceptually correct but won't happen
> > in current KVM design. Above either leads to direct access to L0's
> > APIC-access page (if L0 VMM enables "virtualized APIC accesses"
> > and maps L1 0xfee00000 to L0 APIC-access page), which doesn't
> > really hold L1's APIC state, or cause nested EPT violation fault into
> > L1 VMM (if L0 VMM disables "virtualized APIC accesses", thus L1
> > 0xfee00000 has no valid mapping in L0 EPT). Of course either way
> > is still broken. The former cannot properly virtualize the L2 APIC,
> > while the latter may confuse the L1 VMM if only APIC-access
> > VM exit is expected. But there is not direct L2 access to L1's APIC
> > state anyway. :-)
>
> Sorry sent too fast. :/ There is no nested EPT fault in the latter
> case - it's caused by L0 EPT instead of L1 EPT. Then L0 VMM will
> emulate the L2 access using L1's APIC, as you described.

As it must do, or something else is dreadfully wrong. If L1 sets up
the VMCS12 extended page tables (or shadow page tables, if EPT is not
enabled in VMCS12) such that L2 can access an MMIO region in L1, then
accesses from L2 to that MMIO region should interact with the
corresponding L1 device.