From: Jim Mattson <jmattson@google.com>
To: Like Xu <like.xu.linux@gmail.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Joerg Roedel <joro@8bytes.org>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
Like Xu <likexu@tencent.com>
Subject: Re: [PATCH 01/11] KVM: x86/pmu: Update comments for AMD gp counters
Date: Wed, 23 Feb 2022 11:50:25 -0800 [thread overview]
Message-ID: <CALMp9eTSyWdDe8yd_g2rp2ipx5CerP8CQ2a0H-1HMZsuxWOpfw@mail.gmail.com> (raw)
In-Reply-To: <20220221115201.22208-2-likexu@tencent.com>
On Mon, Feb 21, 2022 at 3:52 AM Like Xu <like.xu.linux@gmail.com> wrote:
>
> From: Like Xu <likexu@tencent.com>
>
> The obsolete comment could more accurately state that AMD platforms
> have two base MSR addresses and two different maximum numbers
> for gp counters, depending on the X86_FEATURE_PERFCTR_CORE feature.
>
> Signed-off-by: Like Xu <likexu@tencent.com>
> ---
> arch/x86/kvm/pmu.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
> index b1a02993782b..c4692f0ff87e 100644
> --- a/arch/x86/kvm/pmu.c
> +++ b/arch/x86/kvm/pmu.c
> @@ -34,7 +34,7 @@
> * However AMD doesn't support fixed-counters;
> * - There are three types of index to access perf counters (PMC):
> * 1. MSR (named msr): For example Intel has MSR_IA32_PERFCTRn and AMD
> - * has MSR_K7_PERFCTRn.
> + * has MSR_F15H_PERF_CTRn or MSR_K7_PERFCTRn.
"Or" sounds exclusive. Maybe it would be better to say:
has MSR_K7_PERFCTRn and, for families 15H and later,
MSR_F15H_PERF_CTRn, where MSR_F15H_PERF_CTR[0-3] are aliased to
MSR_K7_PERFCTRn.
next prev parent reply other threads:[~2022-02-23 19:50 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-21 11:51 [PATCH 00/11] KVM: x86/pmu: Get rid of PERF_TYPE_HARDWAR and other minor fixes Like Xu
2022-02-21 11:51 ` [PATCH 01/11] KVM: x86/pmu: Update comments for AMD gp counters Like Xu
2022-02-23 19:50 ` Jim Mattson [this message]
2022-02-21 11:51 ` [PATCH 02/11] KVM: x86/pmu: Extract check_pmu_event_filter() from the same semantics Like Xu
2022-02-21 11:51 ` [PATCH 03/11] KVM: x86/pmu: Pass only "struct kvm_pmc *pmc" to reprogram_counter() Like Xu
2022-02-21 11:51 ` [PATCH 04/11] KVM: x86/pmu: Drop "u64 eventsel" for reprogram_gp_counter() Like Xu
2022-02-21 11:51 ` [PATCH 05/11] KVM: x86/pmu: Drop "u8 ctrl, int idx" for reprogram_fixed_counter() Like Xu
2022-02-21 11:51 ` [PATCH 06/11] KVM: x86/pmu: Use only the uniformly exported interface reprogram_counter() Like Xu
2022-02-21 11:51 ` [PATCH 07/11] KVM: x86/pmu: Use PERF_TYPE_RAW to merge reprogram_{gp, fixed}counter() Like Xu
2022-02-21 11:51 ` [PATCH 08/11] perf: x86/core: Add interface to query perfmon_event_map[] directly Like Xu
2022-02-21 11:51 ` [PATCH 09/11] KVM: x86/pmu: Replace pmc_perf_hw_id() with perf_get_hw_event_config() Like Xu
2022-02-21 20:57 ` kernel test robot
2022-02-21 11:52 ` [PATCH 10/11] KVM: x86/pmu: Drop amd_event_mapping[] in the KVM context Like Xu
2022-02-21 11:52 ` [PATCH 11/11] KVM: x86/pmu: Protect kvm->arch.pmu_event_filter with SRCU Like Xu
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