From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EAABC00140 for ; Fri, 5 Aug 2022 16:17:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241038AbiHEQRs (ORCPT ); Fri, 5 Aug 2022 12:17:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231545AbiHEQRr (ORCPT ); Fri, 5 Aug 2022 12:17:47 -0400 Received: from mail-yw1-x112b.google.com (mail-yw1-x112b.google.com [IPv6:2607:f8b0:4864:20::112b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6418248E95 for ; Fri, 5 Aug 2022 09:17:46 -0700 (PDT) Received: by mail-yw1-x112b.google.com with SMTP id 00721157ae682-31f661b3f89so28515427b3.11 for ; Fri, 05 Aug 2022 09:17:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=atishpatra.org; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc; bh=eU9F5KTyLXS6Ehm35W4ZJ4KkazoKzToP1yWNY4wU9Kg=; b=OTIMcxvVmtHvZYnx9w+o/IIVHMVnFTjtZpg0iBHBJF/Skq2sQZgscB+aLiUJLN0sfj ysp6VTKukTmrHLmujjUvOzPbY2bFxqoHBmuaRFR/pAJBoyv7X1Nu520OafIyx6Qr6bOV +R3D5siCAJFSmOozQy6OIy6w4KtvhRp01pfrA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc; bh=eU9F5KTyLXS6Ehm35W4ZJ4KkazoKzToP1yWNY4wU9Kg=; b=BccEsY+w+lpDP63Pg79PKnX3nfzSRptTXIdbiAov0J0qBYNyEWKFZtv50BLlFBY/P2 4suqzgZyzUPJt3n5SjnCj4wQrQyKKv+3V+Yr9UB7SeP7LtMlDNnvYrpqSeTHqipJ+6Nb 0HISMSZQo96R+cozsQ5rF23YT7TRrEPnQlyJ6Gr+vnLzewzoUJF5qm+ITIRkNPwAItnL /Ts59YBi2pI7ycjqCJP+C0G00xZRw9vL4DA0eqW8bgyKo3ZvmdwUuMJfWClrGzX0fXoy 7bp3t4pRJjISOigX+81+HOeNmFTK6w5wLDkh+yexFS9foxEzF6loXlIY9VO3oC4pVh53 GCcA== X-Gm-Message-State: ACgBeo3rpiyRkNO8nIQ5VfRf5lzPddEtZKz/NsZN4TkutLgeHMofUxTD k0J10xPE9JyxdKWJzDpqgldJ77onar5FqCbrNTmN X-Google-Smtp-Source: AA6agR62cKws3SRTlgdcM1pts0cZpN6r3mdMoI/TrJcr4NwaVIxxT+6rUb3vilx/LYfVks/NtNXlI1usDhozpgqRr64= X-Received: by 2002:a81:5251:0:b0:31f:56c6:b69 with SMTP id g78-20020a815251000000b0031f56c60b69mr6801352ywb.75.1659716265625; Fri, 05 Aug 2022 09:17:45 -0700 (PDT) MIME-Version: 1.0 References: <20220722165047.519994-1-atishp@rivosinc.com> <20220722165047.519994-4-atishp@rivosinc.com> In-Reply-To: From: Atish Patra Date: Fri, 5 Aug 2022 09:17:35 -0700 Message-ID: Subject: Re: [PATCH v7 3/4] RISC-V: Prefer sstc extension if available To: Stephen Boyd , Palmer Dabbelt , Palmer Dabbelt Cc: "linux-kernel@vger.kernel.org List" , Atish Patra , Anup Patel , Albert Ou , Daniel Lezcano , Guo Ren , Heiko Stuebner , "open list:KERNEL VIRTUAL MACHINE FOR RISC-V (KVM/riscv)" , KVM General , linux-riscv , Paolo Bonzini , Paul Walmsley , Rob Herring , Thomas Gleixner , Tsukasa OI , Wei Fu Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Mon, Jul 25, 2022 at 10:49 PM Atish Patra wrote: > > On Fri, Jul 22, 2022 at 9:50 AM Atish Patra wrote: > > > > RISC-V ISA has sstc extension which allows updating the next clock event > > via a CSR (stimecmp) instead of an SBI call. This should happen dynamically > > if sstc extension is available. Otherwise, it will fallback to SBI call > > to maintain backward compatibility. > > > > Reviewed-by: Anup Patel > > Signed-off-by: Atish Patra > > --- > > drivers/clocksource/timer-riscv.c | 25 ++++++++++++++++++++++++- > > 1 file changed, 24 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c > > index 593d5a957b69..05f6cf067289 100644 > > --- a/drivers/clocksource/timer-riscv.c > > +++ b/drivers/clocksource/timer-riscv.c > > @@ -7,6 +7,9 @@ > > * either be read from the "time" and "timeh" CSRs, and can use the SBI to > > * setup events, or directly accessed using MMIO registers. > > */ > > + > > +#define pr_fmt(fmt) "riscv-timer: " fmt > > + > > #include > > #include > > #include > > @@ -20,14 +23,28 @@ > > #include > > #include > > #include > > +#include > > #include > > #include > > > > +static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available); > > + > > static int riscv_clock_next_event(unsigned long delta, > > struct clock_event_device *ce) > > { > > + u64 next_tval = get_cycles64() + delta; > > + > > csr_set(CSR_IE, IE_TIE); > > - sbi_set_timer(get_cycles64() + delta); > > + if (static_branch_likely(&riscv_sstc_available)) { > > +#if defined(CONFIG_32BIT) > > + csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF); > > + csr_write(CSR_STIMECMPH, next_tval >> 32); > > +#else > > + csr_write(CSR_STIMECMP, next_tval); > > +#endif > > + } else > > + sbi_set_timer(next_tval); > > + > > return 0; > > } > > > > @@ -165,6 +182,12 @@ static int __init riscv_timer_init_dt(struct device_node *n) > > if (error) > > pr_err("cpu hp setup state failed for RISCV timer [%d]\n", > > error); > > + > > + if (riscv_isa_extension_available(NULL, SSTC)) { > > + pr_info("Timer interrupt in S-mode is available via sstc extension\n"); > > + static_branch_enable(&riscv_sstc_available); > > + } > > + > > return error; > > } > > > > -- > > 2.25.1 > > > > Hi Stephen, > Can you please review this whenever you get a chance ? We probably > need an ACK at least :) > Ping ? > -- > Regards, > Atish -- Regards, Atish