From: Sean Christopherson <seanjc@google.com>
To: Jim Mattson <jmattson@google.com>
Cc: Wanpeng Li <kernellwp@gmail.com>,
LKML <linux-kernel@vger.kernel.org>,
kvm list <kvm@vger.kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Joerg Roedel <joro@8bytes.org>
Subject: Re: [PATCH 2/2] KVM: LAPIC: reset TMCCT during vCPU reset
Date: Thu, 3 Jun 2021 15:34:36 +0000 [thread overview]
Message-ID: <YLj2jDKMYZatdl3a@google.com> (raw)
In-Reply-To: <CALMp9eSK-_xOp=WdRbOOHaHHMHuJkPhG+7h4M+_+=4d-GCNzwA@mail.gmail.com>
On Thu, Jun 03, 2021, Jim Mattson wrote:
> On Thu, Jun 3, 2021 at 2:01 AM Wanpeng Li <kernellwp@gmail.com> wrote:
> >
> > From: Wanpeng Li <wanpengli@tencent.com>
> >
> > The value of current counter register after reset is 0 for both Intel
> > and AMD, let's do it in kvm.
> >
> > Signed-off-by: Wanpeng Li <wanpengli@tencent.com>
>
> How did we miss that?
I suspect it's not actually a functional issue, and that writing '0' at reset is
a glorified nop. The TMCCT is always computed on-demand and never directly
readable.
Is there an observable bug being fixed? If not, the changelog should state that
this is a cosmetic change of sorts.
static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
{
u32 val = 0;
if (offset >= LAPIC_MMIO_LENGTH)
return 0;
switch (offset) {
case APIC_ARBPRI:
break;
case APIC_TMCCT: /* Timer CCR */
if (apic_lvtt_tscdeadline(apic))
return 0;
val = apic_get_tmcct(apic);
break;
...
}
static u32 apic_get_tmcct(struct kvm_lapic *apic)
{
ktime_t remaining, now;
s64 ns;
u32 tmcct;
ASSERT(apic != NULL);
/* if initial count is 0, current count should also be 0 */
if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 || <------------
apic->lapic_timer.period == 0)
return 0;
now = ktime_get();
remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
if (ktime_to_ns(remaining) < 0)
remaining = 0;
ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
tmcct = div64_u64(ns,
(APIC_BUS_CYCLE_NS * apic->divide_count));
return tmcct;
}
int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
{
memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
/*
* Get calculated timer current count for remaining timer period (if
* any) and store it in the returned register set.
*/
__kvm_lapic_set_reg(s->regs, APIC_TMCCT,
__apic_read(vcpu->arch.apic, APIC_TMCCT)); <----
return kvm_apic_state_fixup(vcpu, s, false);
}
next prev parent reply other threads:[~2021-06-03 15:34 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-03 9:00 [PATCH 1/2] KVM: LAPIC: write 0 to TMICT should also cancel vmx-preemption timer Wanpeng Li
2021-06-03 9:00 ` [PATCH 2/2] KVM: LAPIC: reset TMCCT during vCPU reset Wanpeng Li
2021-06-03 12:27 ` Jim Mattson
2021-06-03 15:34 ` Sean Christopherson [this message]
2021-06-08 0:31 ` Wanpeng Li
2021-06-03 15:20 ` [PATCH 1/2] KVM: LAPIC: write 0 to TMICT should also cancel vmx-preemption timer Sean Christopherson
2021-06-04 0:36 ` Wanpeng Li
2021-06-04 15:37 ` Sean Christopherson
2021-06-08 0:30 ` Wanpeng Li
2021-06-03 23:02 ` David Matlack
2021-06-04 0:32 ` Wanpeng Li
2021-06-04 15:59 ` David Matlack
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