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[184.144.111.238]) by smtp.gmail.com with ESMTPSA id d4sm735084qty.15.2021.07.30.08.45.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jul 2021 08:45:54 -0700 (PDT) Date: Fri, 30 Jul 2021 11:45:53 -0400 From: Peter Xu To: Sean Christopherson Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Maxim Levitsky , Vitaly Kuznetsov , Paolo Bonzini Subject: Re: [PATCH v2 8/9] KVM: X86: Optimize pte_list_desc with per-array counter Message-ID: References: <20210625153214.43106-1-peterx@redhat.com> <20210625153415.43620-1-peterx@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Wed, Jul 28, 2021 at 09:04:30PM +0000, Sean Christopherson wrote: > > struct pte_list_desc { > > u64 *sptes[PTE_LIST_EXT]; > > + /* > > + * Stores number of entries stored in the pte_list_desc. No need to be > > + * u64 but just for easier alignment. When PTE_LIST_EXT, means full. > > + */ > > + u64 spte_count; > > Per my feedback to the previous patch, this should be above sptes[] so that rmaps > with <8 SPTEs only touch one cache line. No idea if it actually matters in > practice, but I can't see how it would harm anything. Since at it, I'll further move "more" to be at the entry too, so I think it optimizes full entries case too. /* * Slight optimization of cacheline layout, by putting `more' and `spte_count' * at the start; then accessing it will only use one single cacheline for * either full (entries==PTE_LIST_EXT) case or entries<=6. */ struct pte_list_desc { struct pte_list_desc *more; /* * Stores number of entries stored in the pte_list_desc. No need to be * u64 but just for easier alignment. When PTE_LIST_EXT, means full. */ u64 spte_count; u64 *sptes[PTE_LIST_EXT]; }; Thanks, -- Peter Xu