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David Alan Gilbert" , tony.luck@intel.com, marcorr@google.com, sathyanarayanan.kuppuswamy@linux.intel.com Subject: Re: [PATCH v8 01/40] x86/compressed/64: detect/setup SEV/SME features earlier in boot Message-ID: References: <20211210154332.11526-1-brijesh.singh@amd.com> <20211210154332.11526-2-brijesh.singh@amd.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: SJ0PR03CA0130.namprd03.prod.outlook.com (2603:10b6:a03:33c::15) To SN6PR10MB2576.namprd10.prod.outlook.com (2603:10b6:805:44::15) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e48e2eff-ea27-4d3d-ff8f-08d9bf5fe4fb X-MS-TrafficTypeDiagnostic: SN6PR10MB2829:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2733; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UEhJK/ywO7Oaie65KBTiK+qgp83vdNS2OOcKXw5aOTs3oCVh2lSQNE/pYrCRld8Qni7yeTopgeCxZJnxyE5OZGUIWvMiDBXSsMBbEUmY1wwwbO3l54n1T8GuqkBriLR0lEKuVfRTQGTb49XiOSqBDGFftkh9t2iU90bIphyMtUI+xrDjpfWViiBjbS+XRkQmKAF4Env7nBmwQ01n4Fq1kdls6Ln0EwBGhRQxddGwV11M6E8KFMXLieHVfUlKSzLaP/BAdVdv+kVO2RTTbcx7/00iQP1h+3XNWvcXqsjz2dn4RkwpHmTHPfon0vc7UvNjrp3mJiaxY1WYaZGJuiiJ65skLGO4dE3vGJEpNc6RKqWdccN0ufeCF2eJKursKbGClNf/ICVzaVhudlPQYiXqQ/5LJ1SBM5Wbtnw+pSBSBXk8Jt5AdU9KCu35PH63t53HJ1mrNjMYqJR4aG60DmmtK5RrYzBgtMWYhdnE8DDYP/xTCsKYgZnz67k2Y2/n1i9X+waiFfVJrVvBqs1XUeWb8drewzjAJCWhFGKHaAyukgg0ZuEyOK0w3AOpLxkg8Hb9kYNroWONgwgpYkn6vYOmB/vnWc0vo9ev0riyPoxSlxn9Dq5oLmQJ5btF1smgb1RU5EuC67GvetAWgk2iAo+wxgwwL956tcTm4i2fM/JA0tYxkoTrMv7GU7Z8qIil2xjfakIb6fK6U6xh9JhnLFtl1m2gOwUu1d8IYq3b7ZDOTCg= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SN6PR10MB2576.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(7916004)(366004)(4326008)(966005)(4001150100001)(508600001)(54906003)(2906002)(8936002)(38100700002)(7406005)(6916009)(316002)(8676002)(86362001)(7416002)(6666004)(6486002)(33716001)(186003)(53546011)(26005)(6506007)(44832011)(6512007)(9686003)(66476007)(5660300002)(66556008)(66946007);DIR:OUT;SFP:1101; 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I am merely suggesting to do something similar > > to avoid the code duplication. > > Try it yourself. If you can come up with something halfway readable and > it builds, I'm willing to take a look. Patch (to be applied on top of sev-snp-v8 branch of https://github.com/AMDESE/linux.git) is attached at the end. Here are a few things I did. 1. Moved all the common code that existed at the begining of sme_enable() and sev_enable() to an inline function named get_pagetable_bit_pos(). 2. sme_enable() was using AMD_SME_BIT and AMD_SEV_BIT, whereas sev_enable() was dealing with raw bits. Moved those definitions to sev.h, and changed sev_enable() to use those definitions. 3. Make consistent use of BIT_ULL. Venu diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index c2bf99522e5e..b44d6b37796e 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -291,6 +291,7 @@ static void enforce_vmpl0(void) void sev_enable(struct boot_params *bp) { unsigned int eax, ebx, ecx, edx; + unsigned long pt_bit_pos; /* Pagetable bit position */ bool snp; /* @@ -299,26 +300,8 @@ void sev_enable(struct boot_params *bp) */ snp = snp_init(bp); - /* Check for the SME/SEV support leaf */ - eax = 0x80000000; - ecx = 0; - native_cpuid(&eax, &ebx, &ecx, &edx); - if (eax < 0x8000001f) - return; - - /* - * Check for the SME/SEV feature: - * CPUID Fn8000_001F[EAX] - * - Bit 0 - Secure Memory Encryption support - * - Bit 1 - Secure Encrypted Virtualization support - * CPUID Fn8000_001F[EBX] - * - Bits 5:0 - Pagetable bit position used to indicate encryption - */ - eax = 0x8000001f; - ecx = 0; - native_cpuid(&eax, &ebx, &ecx, &edx); - /* Check whether SEV is supported */ - if (!(eax & BIT(1))) { + /* Get the pagetable bit position if SEV is supported */ + if ((get_pagetable_bit_pos(&pt_bit_pos, AMD_SEV_BIT)) < 0) { if (snp) error("SEV-SNP support indicated by CC blob, but not CPUID."); return; @@ -350,7 +333,7 @@ void sev_enable(struct boot_params *bp) if (snp && !(sev_status & MSR_AMD64_SEV_SNP_ENABLED)) error("SEV-SNP supported indicated by CC blob, but not SEV status MSR."); - sme_me_mask = BIT_ULL(ebx & 0x3f); + sme_me_mask = BIT_ULL(pt_bit_pos); } /* Search for Confidential Computing blob in the EFI config table. */ diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 2c5f12ae7d04..41b096f28d02 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -224,6 +224,43 @@ static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, : "memory"); } +/* + * Returns the pagetable bit position in pt_bit_pos, + * iff the specified features are supported. + */ +static inline int get_pagetable_bit_pos(unsigned long *pt_bit_pos, + unsigned long features) +{ + unsigned int eax, ebx, ecx, edx; + + /* Check for the SME/SEV support leaf */ + eax = 0x80000000; + ecx = 0; + native_cpuid(&eax, &ebx, &ecx, &edx); + if (eax < 0x8000001f) + return -1; + + eax = 0x8000001f; + ecx = 0; + native_cpuid(&eax, &ebx, &ecx, &edx); + + /* Check whether the specified features are supported. + * SME/SEV features: + * CPUID Fn8000_001F[EAX] + * - Bit 0 - Secure Memory Encryption support + * - Bit 1 - Secure Encrypted Virtualization support + */ + if (!(eax & features)) + return -1; + + /* + * CPUID Fn8000_001F[EBX] + * - Bits 5:0 - Pagetable bit position used to indicate encryption + */ + *pt_bit_pos = (unsigned long)(ebx & 0x3f); + return 0; +} + #define native_cpuid_reg(reg) \ static inline unsigned int native_cpuid_##reg(unsigned int op) \ { \ diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 7a5934af9d47..1a2344362ec6 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -17,6 +17,9 @@ #define GHCB_PROTOCOL_MAX 2ULL #define GHCB_DEFAULT_USAGE 0ULL +#define AMD_SME_BIT BIT(0) +#define AMD_SEV_BIT BIT(1) + #define VMGEXIT() { asm volatile("rep; vmmcall\n\r"); } enum es_result { diff --git a/arch/x86/mm/mem_encrypt_identity.c b/arch/x86/mm/mem_encrypt_identity.c index 2f723e106ed3..1ef50e969efd 100644 --- a/arch/x86/mm/mem_encrypt_identity.c +++ b/arch/x86/mm/mem_encrypt_identity.c @@ -508,38 +508,18 @@ void __init sme_enable(struct boot_params *bp) unsigned long feature_mask; bool active_by_default; unsigned long me_mask; + unsigned long pt_bit_pos; /* Pagetable bit position */ char buffer[16]; bool snp; u64 msr; snp = snp_init(bp); - /* Check for the SME/SEV support leaf */ - eax = 0x80000000; - ecx = 0; - native_cpuid(&eax, &ebx, &ecx, &edx); - if (eax < 0x8000001f) + /* Get the pagetable bit position if SEV or SME are supported */ + if ((get_pagetable_bit_pos(&pt_bit_pos, AMD_SEV_BIT | AMD_SME_BIT)) < 0) return; -#define AMD_SME_BIT BIT(0) -#define AMD_SEV_BIT BIT(1) - - /* - * Check for the SME/SEV feature: - * CPUID Fn8000_001F[EAX] - * - Bit 0 - Secure Memory Encryption support - * - Bit 1 - Secure Encrypted Virtualization support - * CPUID Fn8000_001F[EBX] - * - Bits 5:0 - Pagetable bit position used to indicate encryption - */ - eax = 0x8000001f; - ecx = 0; - native_cpuid(&eax, &ebx, &ecx, &edx); - /* Check whether SEV or SME is supported */ - if (!(eax & (AMD_SEV_BIT | AMD_SME_BIT))) - return; - - me_mask = 1UL << (ebx & 0x3f); + me_mask = BIT_ULL(pt_bit_pos); /* Check the SEV MSR whether SEV or SME is enabled */ sev_status = __rdmsr(MSR_AMD64_SEV);