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David Alan Gilbert" , tony.luck@intel.com, marcorr@google.com, sathyanarayanan.kuppuswamy@linux.intel.com Subject: Re: [PATCH v8 01/40] x86/compressed/64: detect/setup SEV/SME features earlier in boot Message-ID: References: <20211210154332.11526-1-brijesh.singh@amd.com> <20211210154332.11526-2-brijesh.singh@amd.com> <20211215174934.tgn3c7c4s3toelbq@amd.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211215174934.tgn3c7c4s3toelbq@amd.com> X-ClientProxiedBy: SA9PR13CA0156.namprd13.prod.outlook.com (2603:10b6:806:28::11) To SN6PR10MB2576.namprd10.prod.outlook.com (2603:10b6:805:44::15) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7e0d5d6b-8c69-4bc6-709e-08d9c004b200 X-MS-TrafficTypeDiagnostic: SN6PR10MB3023:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GtEdHxA27a5ifK3Lnd8v+9PfjHtjyQk1n6aJ0XqeuDzcB4C28+qsKW50izL909tbw6s+PgKissJCOVb6NjSAAaJIohL5ALjkqzhdInee9fGdDXm+QezSwMrtB3ukHolCVR9OwFKFlFeU5d7stdZPxPhpsxrKHgMdw7AS5vEiq7CD5m4VXFxPag6OYQz8acnUtoRMVyhVEYTpNeu9NCYVkpB+ySTYWFZUVckcmRZzJ4sUmkAo3soi5fpdiObtgqpRqLhCaZRwujx4CR33HDnDpilJarMD265ulZiaJHFFi5FnDtHQpDDuFdBkdYijgaPN9Yx+G7ILsipxmmxwCTfBSQKMdzQswEGXW8mape1V5lNrmzlJrqBeLfL1Ut+MsWtEI68IEkaZBQsADz2OTRnnFmxpsR+WfhzQ2h7akCoNh85at/vxE7KyGRvl04XG8x57fZWkSHrxxFgblNjcasGQhTy55EXnxzu3qJIotaFNmsNn5JBa1H695HFPasFHiHMjIYkGpZLntjIuu8g0idPqp3ntrjVncOXZ4mzR5bX+90ZkMWht235dUrkiOhh82WlsDh/yk0Ng0sMlSYoL0H83/ApK2taXRB2YNOP0w2owmZ69B7CGih/tJu0smLHn1id94tG2osOoLc7Jc4c6Hbf/Ag== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SN6PR10MB2576.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(7916004)(366004)(186003)(54906003)(4001150100001)(26005)(33716001)(2906002)(6916009)(66476007)(7406005)(6486002)(6512007)(5660300002)(9686003)(53546011)(44832011)(8936002)(8676002)(7416002)(6506007)(316002)(4326008)(508600001)(66556008)(6666004)(66946007)(86362001)(38100700002);DIR:OUT;SFP:1101; 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Implemented using this suggestion, and the patch is at the end. I feel that passing of "true" or "false" to get_me_bit_pos() from sev_enable() and sme_enable() has become less clear now. It is not obvious what the "true" and "false" values mean. However, both implementations (Tom's suggestions and Tom's + Mike's suggestions) are available now. We can pick one of these, or I will redo this if we want a different implementation. Venu --- diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 7a5934af9d47..eb202096a1fc 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -17,6 +17,48 @@ #define GHCB_PROTOCOL_MAX 2ULL #define GHCB_DEFAULT_USAGE 0ULL +#define AMD_SME_BIT BIT(0) +#define AMD_SEV_BIT BIT(1) + +/* + * Returns the memory encryption bit position, + * if the specified features are supported. + * Returns 0, otherwise. + */ +static inline unsigned int get_me_bit_pos(bool sev_only) +{ + unsigned int eax, ebx, ecx, edx; + unsigned int features; + + features = AMD_SEV_BIT | (sev_only ? 0 : AMD_SME_BIT); + + /* Check for the SME/SEV support leaf */ + eax = 0x80000000; + ecx = 0; + native_cpuid(&eax, &ebx, &ecx, &edx); + if (eax < 0x8000001f) + return 0; + + eax = 0x8000001f; + ecx = 0; + native_cpuid(&eax, &ebx, &ecx, &edx); + + /* Check whether the specified features are supported. + * SME/SEV features: + * CPUID Fn8000_001F[EAX] + * - Bit 0 - Secure Memory Encryption support + * - Bit 1 - Secure Encrypted Virtualization support + */ + if (!(eax & features)) + return 0; + + /* + * CPUID Fn8000_001F[EBX] + * - Bits 5:0 - Pagetable bit position used to indicate encryption + */ + return ebx & 0x3f; +} + #define VMGEXIT() { asm volatile("rep; vmmcall\n\r"); } enum es_result { diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index c2bf99522e5e..9a8181893af7 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -291,6 +291,7 @@ static void enforce_vmpl0(void) void sev_enable(struct boot_params *bp) { unsigned int eax, ebx, ecx, edx; + unsigned int me_bit_pos; bool snp; /* @@ -299,26 +300,9 @@ void sev_enable(struct boot_params *bp) */ snp = snp_init(bp); - /* Check for the SME/SEV support leaf */ - eax = 0x80000000; - ecx = 0; - native_cpuid(&eax, &ebx, &ecx, &edx); - if (eax < 0x8000001f) - return; - - /* - * Check for the SME/SEV feature: - * CPUID Fn8000_001F[EAX] - * - Bit 0 - Secure Memory Encryption support - * - Bit 1 - Secure Encrypted Virtualization support - * CPUID Fn8000_001F[EBX] - * - Bits 5:0 - Pagetable bit position used to indicate encryption - */ - eax = 0x8000001f; - ecx = 0; - native_cpuid(&eax, &ebx, &ecx, &edx); - /* Check whether SEV is supported */ - if (!(eax & BIT(1))) { + /* Get the memory encryption bit position if SEV is supported */ + me_bit_pos = get_me_bit_pos(true); + if (!me_bit_pos) { if (snp) error("SEV-SNP support indicated by CC blob, but not CPUID."); return; @@ -350,7 +334,7 @@ void sev_enable(struct boot_params *bp) if (snp && !(sev_status & MSR_AMD64_SEV_SNP_ENABLED)) error("SEV-SNP supported indicated by CC blob, but not SEV status MSR."); - sme_me_mask = BIT_ULL(ebx & 0x3f); + sme_me_mask = BIT_ULL(me_bit_pos); } /* Search for Confidential Computing blob in the EFI config table. */ diff --git a/arch/x86/mm/mem_encrypt_identity.c b/arch/x86/mm/mem_encrypt_identity.c index 2f723e106ed3..a4979f61ecc7 100644 --- a/arch/x86/mm/mem_encrypt_identity.c +++ b/arch/x86/mm/mem_encrypt_identity.c @@ -508,38 +508,19 @@ void __init sme_enable(struct boot_params *bp) unsigned long feature_mask; bool active_by_default; unsigned long me_mask; + unsigned int me_bit_pos; char buffer[16]; bool snp; u64 msr; snp = snp_init(bp); - /* Check for the SME/SEV support leaf */ - eax = 0x80000000; - ecx = 0; - native_cpuid(&eax, &ebx, &ecx, &edx); - if (eax < 0x8000001f) + /* Get the memory encryption bit position if SEV or SME are supported */ + me_bit_pos = get_me_bit_pos(false); + if (!me_bit_pos) return; -#define AMD_SME_BIT BIT(0) -#define AMD_SEV_BIT BIT(1) - - /* - * Check for the SME/SEV feature: - * CPUID Fn8000_001F[EAX] - * - Bit 0 - Secure Memory Encryption support - * - Bit 1 - Secure Encrypted Virtualization support - * CPUID Fn8000_001F[EBX] - * - Bits 5:0 - Pagetable bit position used to indicate encryption - */ - eax = 0x8000001f; - ecx = 0; - native_cpuid(&eax, &ebx, &ecx, &edx); - /* Check whether SEV or SME is supported */ - if (!(eax & (AMD_SEV_BIT | AMD_SME_BIT))) - return; - - me_mask = 1UL << (ebx & 0x3f); + me_mask = BIT_ULL(me_bit_pos); /* Check the SEV MSR whether SEV or SME is enabled */ sev_status = __rdmsr(MSR_AMD64_SEV);