From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9049AC433EF for ; Fri, 4 Feb 2022 10:58:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245163AbiBDK6e (ORCPT ); Fri, 4 Feb 2022 05:58:34 -0500 Received: from foss.arm.com ([217.140.110.172]:35034 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230164AbiBDK6d (ORCPT ); Fri, 4 Feb 2022 05:58:33 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 338E22B; Fri, 4 Feb 2022 02:58:33 -0800 (PST) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6062B3F774; Fri, 4 Feb 2022 02:58:30 -0800 (PST) Date: Fri, 4 Feb 2022 10:58:40 +0000 From: Alexandru Elisei To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Andre Przywara , Christoffer Dall , Jintack Lim , Haibo Xu , Ganapatrao Kulkarni , Chase Conklin , "Russell King (Oracle)" , James Morse , Suzuki K Poulose , karl.heubaum@oracle.com, mihai.carabas@oracle.com, miguel.luis@oracle.com, kernel-team@android.com Subject: Re: [PATCH v6 19/64] KVM: arm64: nv: Trap SPSR_EL1, ELR_EL1 and VBAR_EL1 from virtual EL2 Message-ID: References: <20220128121912.509006-1-maz@kernel.org> <20220128121912.509006-20-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220128121912.509006-20-maz@kernel.org> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Hi Marc, On Fri, Jan 28, 2022 at 12:18:27PM +0000, Marc Zyngier wrote: > From: Jintack Lim > > For the same reason we trap virtual memory register accesses at virtual > EL2, we need to trap SPSR_EL1, ELR_EL1 and VBAR_EL1 accesses. ARM v8.3 > introduces the HCR_EL2.NV1 bit to be able to trap on those register > accesses in EL1. Do not set this bit until the whole nesting support is > completed. > > Signed-off-by: Jintack Lim > Signed-off-by: Marc Zyngier > --- > arch/arm64/kvm/sys_regs.c | 29 ++++++++++++++++++++++++++++- > 1 file changed, 28 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 9d3520f1d17a..4f2bcc1e0c25 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -1650,6 +1650,30 @@ static bool access_sp_el1(struct kvm_vcpu *vcpu, > return true; > } > > +static bool access_elr(struct kvm_vcpu *vcpu, > + struct sys_reg_params *p, > + const struct sys_reg_desc *r) > +{ > + if (p->is_write) > + vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); > + else > + p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); Going over the patch again, I was a bit confused why access_elr() uses vcpu_{read,write}_sys_reg(), but access_spsr() uses __vcpu_sys_reg(). In the end, vcpu_{read,write}_sys_reg() will write to the shadow copy of the registers, as the guest is executing at virtual non-VHE EL2, so the two are equivalent. It's obviously me nitpicking, but the inconsistency is unexpected. How about using vcpu_{read,write}_sys_reg() for access_spsr() below? Thanks, Alex > + > + return true; > +} > + > +static bool access_spsr(struct kvm_vcpu *vcpu, > + struct sys_reg_params *p, > + const struct sys_reg_desc *r) > +{ > + if (p->is_write) > + __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval; > + else > + p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); > + > + return true; > +} > + > static bool access_spsr_el2(struct kvm_vcpu *vcpu, > struct sys_reg_params *p, > const struct sys_reg_desc *r) > @@ -1812,6 +1836,9 @@ static const struct sys_reg_desc sys_reg_descs[] = { > PTRAUTH_KEY(APDB), > PTRAUTH_KEY(APGA), > > + { SYS_DESC(SYS_SPSR_EL1), access_spsr}, > + { SYS_DESC(SYS_ELR_EL1), access_elr}, > + > { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, > { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, > { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, > @@ -1859,7 +1886,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { > { SYS_DESC(SYS_LORC_EL1), trap_loregion }, > { SYS_DESC(SYS_LORID_EL1), trap_loregion }, > > - { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 }, > + { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, > { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, > > { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, > -- > 2.30.2 >