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[34.168.104.7]) by smtp.gmail.com with ESMTPSA id u4-20020a17090a1f0400b001fa79c1de15sm3640192pja.24.2022.08.25.08.23.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Aug 2022 08:23:30 -0700 (PDT) Date: Thu, 25 Aug 2022 15:23:26 +0000 From: Sean Christopherson To: Xiaoyao Li Cc: Peter Zijlstra , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Paolo Bonzini , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [RFC PATCH 1/2] perf/x86/intel/pt: Introduce intel_pt_{stop,resume}() Message-ID: References: <20220825085625.867763-1-xiaoyao.li@intel.com> <20220825085625.867763-2-xiaoyao.li@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220825085625.867763-2-xiaoyao.li@intel.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Thu, Aug 25, 2022, Xiaoyao Li wrote: > KVM supports PT_MODE_HOST_GUEST mode for Intel PT that host and guest > have separate Intel PT configurations and work independently. In that > mdoe, KVM needs to context switch all the Intel PT configurations > between host and guest on VM-entry and VM-exit. > > Before VM-entry, if Intel PT is enabled on host, KVM needs to disable it > first so as to context switch the PT configurations. After VM exit, KVM > needs to re-enable Intel PT for host. Currently, KVM achieves it by > manually toggle MSR_IA32_RTIT_CTL.TRACEEN bit to en/dis-able Intel PT. > > However, PT PMI can be delivered after MSR_IA32_RTIT_CTL.TRACEEN bit is > cleared. PT PMI handler changes PT MSRs and re-enable PT, that leads to > 1) VM-entry failure of guest 2) KVM stores stale value of PT MSRs. > > To solve the problems, expose two interfaces for KVM to stop and > resume the PT tracing. > > Signed-off-by: Xiaoyao Li > --- > arch/x86/events/intel/pt.c | 11 ++++++++++- > arch/x86/include/asm/intel_pt.h | 6 ++++-- > arch/x86/kernel/crash.c | 4 ++-- > 3 files changed, 16 insertions(+), 5 deletions(-) > > diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c > index 82ef87e9a897..55fc02036ff1 100644 > --- a/arch/x86/events/intel/pt.c > +++ b/arch/x86/events/intel/pt.c > @@ -1730,13 +1730,22 @@ static int pt_event_init(struct perf_event *event) > return 0; > } > > -void cpu_emergency_stop_pt(void) > +void intel_pt_stop(void) > { > struct pt *pt = this_cpu_ptr(&pt_ctx); > > if (pt->handle.event) > pt_event_stop(pt->handle.event, PERF_EF_UPDATE); > } > +EXPORT_SYMBOL_GPL(intel_pt_stop); > + > +void intel_pt_resume(void) { Curly brace goes on its own line. > + struct pt *pt = this_cpu_ptr(&pt_ctx); > + > + if (pt->handle.event) > + pt_event_start(pt->handle.event, 0); > +} > +EXPORT_SYMBOL_GPL(intel_pt_resume); > > int is_intel_pt_event(struct perf_event *event) > {