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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?B7YT7g/U3twAjgBc511GwHhz3AzWZcCbIu72SMskLihuRZwmGsasS0XZ2U4m?= =?us-ascii?Q?LFacukZ+YCiWGxH+8ty3HI9iZCSnrKS0koInLiCXUvs5A7jrcBW6Pj4FcbUJ?= =?us-ascii?Q?WWaGCdJwbswhLJcPptIaT4kPgDU+XqYAi6nA0o471SLuhckgT3/imblcTqdp?= =?us-ascii?Q?dVkEiw4mO6IEWmMr4A1Pc1xkgRAsx5MTm0WH8eWEOp1WIcnya1BR7ihWAr62?= =?us-ascii?Q?J/vu+f1LQLcAY67y/POdCy4ouVm372pSthBMsq5D6E9E6qIWunnlPXbCB04f?= =?us-ascii?Q?8dpQNGqhjKabgcIkZzbv66OT2HVLlKreOnUZ5r2YnvMiObyy8WaG+OK0Wb1Z?= =?us-ascii?Q?W85/YDmEXF2lW4sDLfJ/cMIAlfVbUwhbQnJ9J4LCZRkUvBClHrw7T8BD1w1X?= =?us-ascii?Q?Igb27RixUkwmzlm8FR5LGOtiJat7DH8s3gjBM8778QiWvw9J4A4ds8XZs/dN?= =?us-ascii?Q?HEFtEByRz7CQqqIDGpl45hSWcMNdB6RmxXbhLu+ByoGIkXGQQBiJ3Kdv3PT5?= =?us-ascii?Q?mcz2hFerfl5HVBm7nvbBe3gCgseXCeRhm5NDoM26X03+tvXHJMatJOZO1t8G?= =?us-ascii?Q?+jcptAIOCivEkzEQaDTLEdHWYPrgNLlCHuOZ7ucqoo+K64FGCzGpTPwBw69P?= =?us-ascii?Q?x06whw3gl93Airo/XAPw4r3aFfR0VtyQQLiMVt6o5i3bDUYfFjx9XydiRhib?= =?us-ascii?Q?MY4fpbhlMABW5GIzUi8HXwe2Wn+iVAFP+purPdgXrnuaTlS90uR8x55z/Xcz?= =?us-ascii?Q?k0OV/SPTnLtxdvWE+RM86nAXFibQ137yiCQFPanUMIoCuA8fYlM5ygRs429M?= =?us-ascii?Q?2nqO3rGKq1+2N85yS1aftya72si1Ixj2bO8M7KEAZcJjIY+eB+v6VwsNRDIh?= =?us-ascii?Q?d6157UQGKHc7iK+GEovSMMMvFYp23d2JAaXp26ArtzmhmhflH6DF1aaQwUCa?= =?us-ascii?Q?f5l5KxDqDkdvzsuXPEh7FfnqRwuHUDglb2ClHIYd0wzN4Xd1PSIO53StaKCL?= =?us-ascii?Q?H5voSEe9WmPxKl1EzPWCBiFpYnfN1I8XXN8enxzBpf7w1UZJfPBjwW1MenVI?= =?us-ascii?Q?9tmbYmG2fpJK5Q+rsvBoLmv6agg/hxWDHLLEVzv0DQOVAiJBAaoNR2h4Ey5M?= =?us-ascii?Q?sybH+cWMGKIfUaLkZzqA+8bDKHhf9Dnpnp1EH73V/8L6+dknmpv2fY3/02FK?= =?us-ascii?Q?TDXKj+AC/4D/lAJT9j2lAWD5vdtFDn5n7RDc7vSp7ig/03+v6k5aCKt7RCla?= =?us-ascii?Q?iK1msWeWFYlcsQsA6L3Yb1YNxwZyZrSWJwNbNOg4AYArktNnnMTiri5oqHo+?= =?us-ascii?Q?suwzOafVTG90uUohGq2GBPCkvvx4wAgIGebw44yPPMUQ6Rx9bvc16HBrPQ0S?= =?us-ascii?Q?SjbOE4JIO1yjVF33cxrlo5QVvXQRTEcrwoJ11MyxergfVui28D+ZAUrKPu0a?= =?us-ascii?Q?PRd86I15QJAvofB8AAKllfnGzm7lDGRZUgvM97u0B4XfW2M4CgOYbMiCF6C9?= =?us-ascii?Q?4glhWjvdu20+yJYxE4ErhT1n1bnGoEMwjLmCNqerXAKh1iX/qpOxMgZrTLnh?= =?us-ascii?Q?44kqpAI3pybLhOmeSgsQpQ87EmuAK/jdcxbOUng/?= X-MS-Exchange-CrossTenant-Network-Message-Id: 74779467-cf8b-4e71-8d52-08dbe3f54a6d X-MS-Exchange-CrossTenant-AuthSource: CH3PR11MB8660.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Nov 2023 03:04:46.3947 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: DwjOVRNMeNntnk7xFh9EDFK3mx2u1bOoca9SG4lKCRNqNNM1V6GvX3s1OX/+L0mFt2OQ7bXM3AbtuPc/e48x7A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR11MB5511 X-OriginatorOrg: intel.com On Wed, Nov 08, 2023 at 10:29:48AM -0800, Xin Li wrote: >Initialize host VMCS FRED fields with host FRED MSRs' value and >guest VMCS FRED fields to 0. > >FRED CPU states are managed in 9 new FRED MSRs, as well as a few >existing CPU registers and MSRs, e.g., CR4.FRED. To support FRED >context management, new VMCS fields corresponding to most of FRED >CPU state MSRs are added to both the host-state and guest-state >areas of VMCS. > >Specifically no VMCS fields are added for FRED RSP0 and SSP0 MSRs, >because the 2 FRED MSRs are used during ring 3 event delivery only, >thus KVM, running on ring 0, can run safely even with guest FRED >RSP0 and SSP0. It can be deferred to load host FRED RSP0 and SSP0 >until before returning to user level. > >Tested-by: Shan Kang >Signed-off-by: Xin Li >--- > arch/x86/include/asm/vmx.h | 16 ++++++++++++++++ > arch/x86/kvm/vmx/vmx.c | 32 ++++++++++++++++++++++++++++++++ > 2 files changed, 48 insertions(+) > >diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h >index 41796a733bc9..d54a1a1057b0 100644 >--- a/arch/x86/include/asm/vmx.h >+++ b/arch/x86/include/asm/vmx.h >@@ -277,12 +277,28 @@ enum vmcs_field { > GUEST_BNDCFGS_HIGH = 0x00002813, > GUEST_IA32_RTIT_CTL = 0x00002814, > GUEST_IA32_RTIT_CTL_HIGH = 0x00002815, >+ GUEST_IA32_FRED_CONFIG = 0x0000281a, >+ GUEST_IA32_FRED_RSP1 = 0x0000281c, >+ GUEST_IA32_FRED_RSP2 = 0x0000281e, >+ GUEST_IA32_FRED_RSP3 = 0x00002820, >+ GUEST_IA32_FRED_STKLVLS = 0x00002822, >+ GUEST_IA32_FRED_SSP1 = 0x00002824, >+ GUEST_IA32_FRED_SSP2 = 0x00002826, >+ GUEST_IA32_FRED_SSP3 = 0x00002828, > HOST_IA32_PAT = 0x00002c00, > HOST_IA32_PAT_HIGH = 0x00002c01, > HOST_IA32_EFER = 0x00002c02, > HOST_IA32_EFER_HIGH = 0x00002c03, > HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04, > HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05, >+ HOST_IA32_FRED_CONFIG = 0x00002c08, >+ HOST_IA32_FRED_RSP1 = 0x00002c0a, >+ HOST_IA32_FRED_RSP2 = 0x00002c0c, >+ HOST_IA32_FRED_RSP3 = 0x00002c0e, >+ HOST_IA32_FRED_STKLVLS = 0x00002c10, >+ HOST_IA32_FRED_SSP1 = 0x00002c12, >+ HOST_IA32_FRED_SSP2 = 0x00002c14, >+ HOST_IA32_FRED_SSP3 = 0x00002c16, > PIN_BASED_VM_EXEC_CONTROL = 0x00004000, > CPU_BASED_VM_EXEC_CONTROL = 0x00004002, > EXCEPTION_BITMAP = 0x00004004, >diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c >index 327e052d90c1..41772ecdd368 100644 >--- a/arch/x86/kvm/vmx/vmx.c >+++ b/arch/x86/kvm/vmx/vmx.c >@@ -1477,6 +1477,18 @@ void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu, > (unsigned long)(cpu_entry_stack(cpu) + 1)); > } > >+#ifdef CONFIG_X86_64 >+ /* Per-CPU FRED MSRs */ >+ if (cpu_feature_enabled(X86_FEATURE_FRED)) { how about kvm_cpu_cap_has()? to decouple KVM's capability to virtualize a feature and host's enabling a feature. >+ vmcs_write64(HOST_IA32_FRED_RSP1, read_msr(MSR_IA32_FRED_RSP1)); >+ vmcs_write64(HOST_IA32_FRED_RSP2, read_msr(MSR_IA32_FRED_RSP2)); >+ vmcs_write64(HOST_IA32_FRED_RSP3, read_msr(MSR_IA32_FRED_RSP3)); >+ vmcs_write64(HOST_IA32_FRED_SSP1, read_msr(MSR_IA32_FRED_SSP1)); >+ vmcs_write64(HOST_IA32_FRED_SSP2, read_msr(MSR_IA32_FRED_SSP2)); >+ vmcs_write64(HOST_IA32_FRED_SSP3, read_msr(MSR_IA32_FRED_SSP3)); >+ } >+#endif why is this hunk enclosed in #ifdef CONFIG_X86_64 while the one below isn't? >+ > vmx->loaded_vmcs->cpu = cpu; > } > } >@@ -4375,6 +4387,15 @@ void vmx_set_constant_host_state(struct vcpu_vmx *vmx) > > if (cpu_has_load_ia32_efer()) > vmcs_write64(HOST_IA32_EFER, host_efer); >+ >+ /* >+ * FRED MSRs are per-cpu, however FRED CONFIG and STKLVLS MSRs >+ * are the same on all CPUs, thus they are initialized here. >+ */ >+ if (cpu_feature_enabled(X86_FEATURE_FRED)) { >+ vmcs_write64(HOST_IA32_FRED_CONFIG, read_msr(MSR_IA32_FRED_CONFIG)); >+ vmcs_write64(HOST_IA32_FRED_STKLVLS, read_msr(MSR_IA32_FRED_STKLVLS)); >+ } > } > > void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) >@@ -4936,6 +4957,17 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) > vmcs_writel(GUEST_IDTR_BASE, 0); > vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); > >+ if (cpu_feature_enabled(X86_FEATURE_FRED)) { >+ vmcs_write64(GUEST_IA32_FRED_CONFIG, 0); >+ vmcs_write64(GUEST_IA32_FRED_RSP1, 0); >+ vmcs_write64(GUEST_IA32_FRED_RSP2, 0); >+ vmcs_write64(GUEST_IA32_FRED_RSP3, 0); >+ vmcs_write64(GUEST_IA32_FRED_STKLVLS, 0); >+ vmcs_write64(GUEST_IA32_FRED_SSP1, 0); >+ vmcs_write64(GUEST_IA32_FRED_SSP2, 0); >+ vmcs_write64(GUEST_IA32_FRED_SSP3, 0); >+ } >+ move this hunk to __vmx_vcpu_reset() because FRED spec says "INIT does not change the value of the new MSRs." > vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); > vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); > vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); >-- >2.42.0 > >