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From: Marc Zyngier <marc.zyngier@arm.com>
To: Alexandru Elisei <alexandru.elisei@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org
Cc: Andre Przywara <andre.przywara@arm.com>,
	Dave Martin <Dave.Martin@arm.com>
Subject: Re: [PATCH 07/59] KVM: arm64: nv: Add EL2 system registers to vcpu context
Date: Wed, 3 Jul 2019 14:20:40 +0100
Message-ID: <a05950b4-400f-4605-6163-2d5611359ff1@arm.com> (raw)
In-Reply-To: <83f3352a-0a9d-3373-87b8-162f2648dc88@arm.com>

On 24/06/2019 16:47, Alexandru Elisei wrote:
> On 6/21/19 10:37 AM, Marc Zyngier wrote:
>> From: Jintack Lim <jintack.lim@linaro.org>
>>
>> ARM v8.3 introduces a new bit in the HCR_EL2, which is the NV bit. When
>> this bit is set, accessing EL2 registers in EL1 traps to EL2. In
>> addition, executing the following instructions in EL1 will trap to EL2:
>> tlbi, at, eret, and msr/mrs instructions to access SP_EL1. Most of the
>> instructions that trap to EL2 with the NV bit were undef at EL1 prior to
>> ARM v8.3. The only instruction that was not undef is eret.
>>
>> This patch sets up a handler for EL2 registers and SP_EL1 register
>> accesses at EL1. The host hypervisor keeps those register values in
>> memory, and will emulate their behavior.
>>
>> This patch doesn't set the NV bit yet. It will be set in a later patch
>> once nested virtualization support is completed.
>>
>> Signed-off-by: Jintack Lim <jintack.lim@linaro.org>
>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>> ---
>>  arch/arm64/include/asm/kvm_host.h | 37 +++++++++++++++-
>>  arch/arm64/include/asm/sysreg.h   | 50 ++++++++++++++++++++-
>>  arch/arm64/kvm/sys_regs.c         | 74 ++++++++++++++++++++++++++++---
>>  3 files changed, 154 insertions(+), 7 deletions(-)
>>
>> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
>> index 4bcd9c1291d5..2d4290d2513a 100644
>> --- a/arch/arm64/include/asm/kvm_host.h
>> +++ b/arch/arm64/include/asm/kvm_host.h
>> @@ -173,12 +173,47 @@ enum vcpu_sysreg {
>>  	APGAKEYLO_EL1,
>>  	APGAKEYHI_EL1,
>>  
>> -	/* 32bit specific registers. Keep them at the end of the range */
>> +	/* 32bit specific registers. */
>>  	DACR32_EL2,	/* Domain Access Control Register */
>>  	IFSR32_EL2,	/* Instruction Fault Status Register */
>>  	FPEXC32_EL2,	/* Floating-Point Exception Control Register */
>>  	DBGVCR32_EL2,	/* Debug Vector Catch Register */
>>  
>> +	/* EL2 registers sorted ascending by Op0, Op1, CRn, CRm, Op2 */
>> +	FIRST_EL2_SYSREG,
>> +	VPIDR_EL2 = FIRST_EL2_SYSREG,
>> +			/* Virtualization Processor ID Register */
>> +	VMPIDR_EL2,	/* Virtualization Multiprocessor ID Register */
>> +	SCTLR_EL2,	/* System Control Register (EL2) */
>> +	ACTLR_EL2,	/* Auxiliary Control Register (EL2) */
>> +	HCR_EL2,	/* Hypervisor Configuration Register */
>> +	MDCR_EL2,	/* Monitor Debug Configuration Register (EL2) */
>> +	CPTR_EL2,	/* Architectural Feature Trap Register (EL2) */
>> +	HSTR_EL2,	/* Hypervisor System Trap Register */
>> +	HACR_EL2,	/* Hypervisor Auxiliary Control Register */
>> +	TTBR0_EL2,	/* Translation Table Base Register 0 (EL2) */
>> +	TTBR1_EL2,	/* Translation Table Base Register 1 (EL2) */
>> +	TCR_EL2,	/* Translation Control Register (EL2) */
>> +	VTTBR_EL2,	/* Virtualization Translation Table Base Register */
>> +	VTCR_EL2,	/* Virtualization Translation Control Register */
>> +	SPSR_EL2,	/* EL2 saved program status register */
>> +	ELR_EL2,	/* EL2 exception link register */
>> +	AFSR0_EL2,	/* Auxiliary Fault Status Register 0 (EL2) */
>> +	AFSR1_EL2,	/* Auxiliary Fault Status Register 1 (EL2) */
>> +	ESR_EL2,	/* Exception Syndrome Register (EL2) */
>> +	FAR_EL2,	/* Hypervisor IPA Fault Address Register */
>> +	HPFAR_EL2,	/* Hypervisor IPA Fault Address Register */
>> +	MAIR_EL2,	/* Memory Attribute Indirection Register (EL2) */
>> +	AMAIR_EL2,	/* Auxiliary Memory Attribute Indirection Register (EL2) */
>> +	VBAR_EL2,	/* Vector Base Address Register (EL2) */
>> +	RVBAR_EL2,	/* Reset Vector Base Address Register */
>> +	RMR_EL2,	/* Reset Management Register */
>> +	CONTEXTIDR_EL2,	/* Context ID Register (EL2) */
>> +	TPIDR_EL2,	/* EL2 Software Thread ID Register */
>> +	CNTVOFF_EL2,	/* Counter-timer Virtual Offset register */
>> +	CNTHCTL_EL2,	/* Counter-timer Hypervisor Control register */
>> +	SP_EL2,		/* EL2 Stack Pointer */
>> +
>>  	NR_SYS_REGS	/* Nothing after this line! */
>>  };
>>  
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index f3ca7e4796ab..8b95f2c42c3d 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -411,17 +411,49 @@
>>  
>>  #define SYS_PMCCFILTR_EL0		sys_reg(3, 3, 14, 15, 7)
>>  
>> +#define SYS_VPIDR_EL2			sys_reg(3, 4, 0, 0, 0)
>> +#define SYS_VMPIDR_EL2			sys_reg(3, 4, 0, 0, 5)
>> +
>> +#define SYS_SCTLR_EL2			sys_reg(3, 4, 1, 0, 0)
>> +#define SYS_ACTLR_EL2			sys_reg(3, 4, 1, 0, 1)
>> +#define SYS_HCR_EL2			sys_reg(3, 4, 1, 1, 0)
>> +#define SYS_MDCR_EL2			sys_reg(3, 4, 1, 1, 1)
>> +#define SYS_CPTR_EL2			sys_reg(3, 4, 1, 1, 2)
>> +#define SYS_HSTR_EL2			sys_reg(3, 4, 1, 1, 3)
>> +#define SYS_HACR_EL2			sys_reg(3, 4, 1, 1, 7)
>> +
>>  #define SYS_ZCR_EL2			sys_reg(3, 4, 1, 2, 0)
>> +
>> +#define SYS_TTBR0_EL2			sys_reg(3, 4, 2, 0, 0)
>> +#define SYS_TTBR1_EL2			sys_reg(3, 4, 2, 0, 1)
>> +#define SYS_TCR_EL2			sys_reg(3, 4, 2, 0, 2)
>> +#define SYS_VTTBR_EL2			sys_reg(3, 4, 2, 1, 0)
>> +#define SYS_VTCR_EL2			sys_reg(3, 4, 2, 1, 2)
>> +
>>  #define SYS_DACR32_EL2			sys_reg(3, 4, 3, 0, 0)
>> +
>>  #define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)
>>  #define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
>> +#define SYS_SP_EL1			sys_reg(3, 4, 4, 1, 0)
>> +
>>  #define SYS_IFSR32_EL2			sys_reg(3, 4, 5, 0, 1)
>> +#define SYS_AFSR0_EL2			sys_reg(3, 4, 5, 1, 0)
>> +#define SYS_AFSR1_EL2			sys_reg(3, 4, 5, 1, 1)
>>  #define SYS_ESR_EL2			sys_reg(3, 4, 5, 2, 0)
>>  #define SYS_VSESR_EL2			sys_reg(3, 4, 5, 2, 3)
>>  #define SYS_FPEXC32_EL2			sys_reg(3, 4, 5, 3, 0)
>>  #define SYS_FAR_EL2			sys_reg(3, 4, 6, 0, 0)
>>  
>> -#define SYS_VDISR_EL2			sys_reg(3, 4, 12, 1,  1)
>> +#define SYS_FAR_EL2			sys_reg(3, 4, 6, 0, 0)
>> +#define SYS_HPFAR_EL2			sys_reg(3, 4, 6, 0, 4)
>> +
>> +#define SYS_MAIR_EL2			sys_reg(3, 4, 10, 2, 0)
>> +#define SYS_AMAIR_EL2			sys_reg(3, 4, 10, 3, 0)
>> +
>> +#define SYS_VBAR_EL2			sys_reg(3, 4, 12, 0, 0)
>> +#define SYS_RVBAR_EL2			sys_reg(3, 4, 12, 0, 1)
>> +#define SYS_RMR_EL2			sys_reg(3, 4, 12, 0, 2)
>> +#define SYS_VDISR_EL2			sys_reg(3, 4, 12, 1, 1)
>>  #define __SYS__AP0Rx_EL2(x)		sys_reg(3, 4, 12, 8, x)
>>  #define SYS_ICH_AP0R0_EL2		__SYS__AP0Rx_EL2(0)
>>  #define SYS_ICH_AP0R1_EL2		__SYS__AP0Rx_EL2(1)
>> @@ -463,23 +495,37 @@
>>  #define SYS_ICH_LR14_EL2		__SYS__LR8_EL2(6)
>>  #define SYS_ICH_LR15_EL2		__SYS__LR8_EL2(7)
>>  
>> +#define SYS_CONTEXTIDR_EL2		sys_reg(3, 4, 13, 0, 1)
>> +#define SYS_TPIDR_EL2			sys_reg(3, 4, 13, 0, 2)
>> +
>> +#define SYS_CNTVOFF_EL2			sys_reg(3, 4, 14, 0, 3)
>> +#define SYS_CNTHCTL_EL2			sys_reg(3, 4, 14, 1, 0)
>> +
>>  /* VHE encodings for architectural EL0/1 system registers */
>>  #define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)
>>  #define SYS_CPACR_EL12			sys_reg(3, 5, 1, 0, 2)
>>  #define SYS_ZCR_EL12			sys_reg(3, 5, 1, 2, 0)
>> +
>>  #define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
>>  #define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
>>  #define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)
>> +
>>  #define SYS_SPSR_EL12			sys_reg(3, 5, 4, 0, 0)
>>  #define SYS_ELR_EL12			sys_reg(3, 5, 4, 0, 1)
>> +
>>  #define SYS_AFSR0_EL12			sys_reg(3, 5, 5, 1, 0)
>>  #define SYS_AFSR1_EL12			sys_reg(3, 5, 5, 1, 1)
>>  #define SYS_ESR_EL12			sys_reg(3, 5, 5, 2, 0)
>> +
>>  #define SYS_FAR_EL12			sys_reg(3, 5, 6, 0, 0)
>> +
>>  #define SYS_MAIR_EL12			sys_reg(3, 5, 10, 2, 0)
>>  #define SYS_AMAIR_EL12			sys_reg(3, 5, 10, 3, 0)
>> +
>>  #define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)
>> +
>>  #define SYS_CONTEXTIDR_EL12		sys_reg(3, 5, 13, 0, 1)
>> +
>>  #define SYS_CNTKCTL_EL12		sys_reg(3, 5, 14, 1, 0)
>>  #define SYS_CNTP_TVAL_EL02		sys_reg(3, 5, 14, 2, 0)
>>  #define SYS_CNTP_CTL_EL02		sys_reg(3, 5, 14, 2, 1)
>> @@ -488,6 +534,8 @@
>>  #define SYS_CNTV_CTL_EL02		sys_reg(3, 5, 14, 3, 1)
>>  #define SYS_CNTV_CVAL_EL02		sys_reg(3, 5, 14, 3, 2)
>>  
>> +#define SYS_SP_EL2			sys_reg(3, 6,  4, 1, 0)
>> +
>>  /* Common SCTLR_ELx flags. */
>>  #define SCTLR_ELx_DSSBS	(_BITUL(44))
>>  #define SCTLR_ELx_ENIA	(_BITUL(31))
>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> index adb8a7e9c8e4..e81be6debe07 100644
>> --- a/arch/arm64/kvm/sys_regs.c
>> +++ b/arch/arm64/kvm/sys_regs.c
>> @@ -184,6 +184,18 @@ static u32 get_ccsidr(u32 csselr)
>>  	return ccsidr;
>>  }
>>  
>> +static bool access_rw(struct kvm_vcpu *vcpu,
>> +		      struct sys_reg_params *p,
>> +		      const struct sys_reg_desc *r)
>> +{
>> +	if (p->is_write)
>> +		vcpu_write_sys_reg(vcpu, p->regval, r->reg);
>> +	else
>> +		p->regval = vcpu_read_sys_reg(vcpu, r->reg);
>> +
>> +	return true;
>> +}
>> +
>>  /*
>>   * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
>>   */
>> @@ -394,12 +406,9 @@ static bool trap_debug_regs(struct kvm_vcpu *vcpu,
>>  			    struct sys_reg_params *p,
>>  			    const struct sys_reg_desc *r)
>>  {
>> -	if (p->is_write) {
>> -		vcpu_write_sys_reg(vcpu, p->regval, r->reg);
>> +	access_rw(vcpu, p, r);
>> +	if (p->is_write)
>>  		vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
>> -	} else {
>> -		p->regval = vcpu_read_sys_reg(vcpu, r->reg);
>> -	}
>>  
>>  	trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
>>  
>> @@ -1354,6 +1363,19 @@ static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>>  	.set_user = set_raz_id_reg,		\
>>  }
>>  
>> +static bool access_sp_el1(struct kvm_vcpu *vcpu,
>> +			  struct sys_reg_params *p,
>> +			  const struct sys_reg_desc *r)
>> +{
>> +	/* SP_EL1 is NOT maintained in sys_regs array */
>> +	if (p->is_write)
>> +		vcpu->arch.ctxt.gp_regs.sp_el1 = p->regval;
>> +	else
>> +		p->regval = vcpu->arch.ctxt.gp_regs.sp_el1;
>> +
>> +	return true;
>> +}
>> +
>>  /*
>>   * Architected system registers.
>>   * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
>> @@ -1646,9 +1668,51 @@ static const struct sys_reg_desc sys_reg_descs[] = {
>>  	 */
>>  	{ SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
> I have to admit I haven't gone through all the patches, or maybe this is part of
> the bits that will be added at a later date, but some of the reset values seem
> incorrect according to ARM DDI 0487D.a. I'll comment below the relevant registers.
>>  
>> +	{ SYS_DESC(SYS_VPIDR_EL2), access_rw, reset_val, VPIDR_EL2, 0 },
>> +	{ SYS_DESC(SYS_VMPIDR_EL2), access_rw, reset_val, VMPIDR_EL2, 0 },
>> +
>> +	{ SYS_DESC(SYS_SCTLR_EL2), access_rw, reset_val, SCTLR_EL2, 0 },
> Some bits are RES1 for SCTLR_EL2.

See Patch #67.
>> +	{ SYS_DESC(SYS_ACTLR_EL2), access_rw, reset_val, ACTLR_EL2, 0 },
>> +	{ SYS_DESC(SYS_HCR_EL2), access_rw, reset_val, HCR_EL2, 0 },
>> +	{ SYS_DESC(SYS_MDCR_EL2), access_rw, reset_val, MDCR_EL2, 0 },
>> +	{ SYS_DESC(SYS_CPTR_EL2), access_rw, reset_val, CPTR_EL2, 0 },
> Some bits are RES1 for CPTR_EL2 if HCR_EL2.E2H == 0, which the reset value for
> HCR_EL2 seems to imply.

Correct.

>> +	{ SYS_DESC(SYS_HSTR_EL2), access_rw, reset_val, HSTR_EL2, 0 },
>> +	{ SYS_DESC(SYS_HACR_EL2), access_rw, reset_val, HACR_EL2, 0 },
>> +
>> +	{ SYS_DESC(SYS_TTBR0_EL2), access_rw, reset_val, TTBR0_EL2, 0 },
>> +	{ SYS_DESC(SYS_TTBR1_EL2), access_rw, reset_val, TTBR1_EL2, 0 },
>> +	{ SYS_DESC(SYS_TCR_EL2), access_rw, reset_val, TCR_EL2, 0 },
> Same here, bits 31 and 23 are RES1 for TCR_EL2 when HCR_EL2.E2H == 0.

Indeed. This requires separate handling altogether.

>> +	{ SYS_DESC(SYS_VTTBR_EL2), access_rw, reset_val, VTTBR_EL2, 0 },
>> +	{ SYS_DESC(SYS_VTCR_EL2), access_rw, reset_val, VTCR_EL2, 0 },
>> +
>>  	{ SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
>> +	{ SYS_DESC(SYS_SPSR_EL2), access_rw, reset_val, SPSR_EL2, 0 },
>> +	{ SYS_DESC(SYS_ELR_EL2), access_rw, reset_val, ELR_EL2, 0 },
>> +	{ SYS_DESC(SYS_SP_EL1), access_sp_el1},
>> +
>>  	{ SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
>> +	{ SYS_DESC(SYS_AFSR0_EL2), access_rw, reset_val, AFSR0_EL2, 0 },
>> +	{ SYS_DESC(SYS_AFSR1_EL2), access_rw, reset_val, AFSR1_EL2, 0 },
>> +	{ SYS_DESC(SYS_ESR_EL2), access_rw, reset_val, ESR_EL2, 0 },
>>  	{ SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
>> +
>> +	{ SYS_DESC(SYS_FAR_EL2), access_rw, reset_val, FAR_EL2, 0 },
>> +	{ SYS_DESC(SYS_HPFAR_EL2), access_rw, reset_val, HPFAR_EL2, 0 },
>> +
>> +	{ SYS_DESC(SYS_MAIR_EL2), access_rw, reset_val, MAIR_EL2, 0 },
>> +	{ SYS_DESC(SYS_AMAIR_EL2), access_rw, reset_val, AMAIR_EL2, 0 },
>> +
>> +	{ SYS_DESC(SYS_VBAR_EL2), access_rw, reset_val, VBAR_EL2, 0 },
>> +	{ SYS_DESC(SYS_RVBAR_EL2), access_rw, reset_val, RVBAR_EL2, 0 },
>> +	{ SYS_DESC(SYS_RMR_EL2), access_rw, reset_val, RMR_EL2, 0 },
> Bit AA64 [0] for RMR_EL2 is RAO/WI for EL2 cannot aarch32, which is what the
> patches seem to enforce.

Yup.

I guess I'll end-up spitting those registers out of this patch and
handle them separately.

>> +
>> +	{ SYS_DESC(SYS_CONTEXTIDR_EL2), access_rw, reset_val, CONTEXTIDR_EL2, 0 },
>> +	{ SYS_DESC(SYS_TPIDR_EL2), access_rw, reset_val, TPIDR_EL2, 0 },
>> +
>> +	{ SYS_DESC(SYS_CNTVOFF_EL2), access_rw, reset_val, CNTVOFF_EL2, 0 },
>> +	{ SYS_DESC(SYS_CNTHCTL_EL2), access_rw, reset_val, CNTHCTL_EL2, 0 },
>> +
>> +	{ SYS_DESC(SYS_SP_EL2), NULL, reset_unknown, SP_EL2 },
>>  };
>>  
>>  static bool trap_dbgidr(struct kvm_vcpu *vcpu,

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

  reply index

Thread overview: 174+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-21  9:37 [PATCH 00/59] KVM: arm64: ARMv8.3 Nested Virtualization support Marc Zyngier
2019-06-21  9:37 ` [PATCH 01/59] KVM: arm64: Migrate _elx sysreg accessors to msr_s/mrs_s Marc Zyngier
2019-06-24 11:16   ` Dave Martin
2019-06-24 12:59   ` Alexandru Elisei
2019-07-03 12:32     ` Marc Zyngier
2019-06-21  9:37 ` [PATCH 02/59] KVM: arm64: Move __load_guest_stage2 to kvm_mmu.h Marc Zyngier
2019-06-24 11:19   ` Dave Martin
2019-07-03  9:30     ` Marc Zyngier
2019-07-03 16:13       ` Dave Martin
2019-06-21  9:37 ` [PATCH 03/59] arm64: Add ARM64_HAS_NESTED_VIRT cpufeature Marc Zyngier
2019-06-21 13:08   ` Julien Thierry
2019-06-21 13:22     ` Marc Zyngier
2019-06-21 13:44   ` Suzuki K Poulose
2019-06-24 11:24   ` Dave Martin
2019-06-21  9:37 ` [PATCH 04/59] KVM: arm64: nv: Introduce nested virtualization VCPU feature Marc Zyngier
2019-06-21 13:08   ` Julien Thierry
2019-06-24 11:28   ` Dave Martin
2019-07-03 11:53     ` Marc Zyngier
2019-07-03 16:27       ` Dave Martin
2019-06-24 11:43   ` Dave Martin
2019-07-03 11:56     ` Marc Zyngier
2019-07-03 16:24       ` Dave Martin
2019-06-21  9:37 ` [PATCH 05/59] KVM: arm64: nv: Reset VCPU to EL2 registers if VCPU nested virt is set Marc Zyngier
2019-06-24 10:19   ` Suzuki K Poulose
2019-06-24 11:38   ` Dave Martin
2019-06-21  9:37 ` [PATCH 06/59] KVM: arm64: nv: Allow userspace to set PSR_MODE_EL2x Marc Zyngier
2019-06-21 13:24   ` Julien Thierry
2019-06-21 13:50     ` Marc Zyngier
2019-06-24 12:48       ` Dave Martin
2019-07-03  9:21         ` Marc Zyngier
2019-07-04 10:00           ` Dave Martin
2019-06-21  9:37 ` [PATCH 07/59] KVM: arm64: nv: Add EL2 system registers to vcpu context Marc Zyngier
2019-06-24 12:54   ` Dave Martin
2019-07-03 12:20     ` Marc Zyngier
2019-07-03 16:31       ` Dave Martin
2019-06-24 15:47   ` Alexandru Elisei
2019-07-03 13:20     ` Marc Zyngier [this message]
2019-07-03 16:01       ` Marc Zyngier
2019-07-01 16:36   ` Suzuki K Poulose
2019-06-21  9:37 ` [PATCH 08/59] KVM: arm64: nv: Reset VMPIDR_EL2 and VPIDR_EL2 to sane values Marc Zyngier
2019-06-24 12:59   ` Dave Martin
2019-06-21  9:37 ` [PATCH 09/59] KVM: arm64: nv: Add nested virt VCPU primitives for vEL2 VCPU state Marc Zyngier
2019-06-24 13:08   ` Dave Martin
2019-06-21  9:37 ` [PATCH 10/59] KVM: arm64: nv: Support virtual EL2 exceptions Marc Zyngier
2019-07-08 13:56   ` Steven Price
2019-06-21  9:37 ` [PATCH 11/59] KVM: arm64: nv: Inject HVC exceptions to the virtual EL2 Marc Zyngier
2019-06-25 13:13   ` Alexandru Elisei
2019-07-03 14:16     ` Marc Zyngier
2019-07-30 14:08     ` Alexandru Elisei
2019-06-21  9:37 ` [PATCH 12/59] KVM: arm64: nv: Handle trapped ERET from " Marc Zyngier
2019-07-02 12:00   ` Alexandru Elisei
2019-06-21  9:37 ` [PATCH 13/59] KVM: arm64: nv: Handle virtual EL2 registers in vcpu_read/write_sys_reg() Marc Zyngier
2019-06-24 12:42   ` Julien Thierry
2019-06-25 14:02     ` Alexandru Elisei
2019-07-03 12:15     ` Marc Zyngier
2019-07-03 15:21       ` Julien Thierry
2019-06-25 15:18   ` Alexandru Elisei
2019-07-01  9:58     ` Alexandru Elisei
2019-07-03 15:59     ` Marc Zyngier
2019-07-03 16:32       ` Alexandru Elisei
2019-07-04 14:39         ` Marc Zyngier
2019-06-26 15:04   ` Alexandru Elisei
2019-07-04 15:05     ` Marc Zyngier
2019-07-01 12:10   ` Alexandru Elisei
2019-06-21  9:37 ` [PATCH 14/59] KVM: arm64: nv: Handle SPSR_EL2 specially Marc Zyngier
2019-06-21  9:37 ` [PATCH 15/59] KVM: arm64: nv: Refactor vcpu_{read,write}_sys_reg Marc Zyngier
2019-06-24 15:07   ` Julien Thierry
2019-07-03 13:09     ` Marc Zyngier
2019-06-27  9:21   ` Alexandru Elisei
2019-07-04 15:15     ` Marc Zyngier
2019-06-21  9:38 ` [PATCH 16/59] KVM: arm64: nv: Save/Restore vEL2 sysregs Marc Zyngier
2019-06-25  8:48   ` Julien Thierry
2019-07-03 13:42     ` Marc Zyngier
2019-07-01 12:09   ` Alexandru Elisei
2019-08-21 11:57   ` Alexandru Elisei
2019-06-21  9:38 ` [PATCH 17/59] KVM: arm64: nv: Emulate PSTATE.M for a guest hypervisor Marc Zyngier
2019-06-21  9:38 ` [PATCH 18/59] KVM: arm64: nv: Trap EL1 VM register accesses in virtual EL2 Marc Zyngier
2019-07-01 16:12   ` Alexandru Elisei
2019-06-21  9:38 ` [PATCH 19/59] KVM: arm64: nv: Trap SPSR_EL1, ELR_EL1 and VBAR_EL1 from " Marc Zyngier
2019-06-21  9:38 ` [PATCH 20/59] KVM: arm64: nv: Trap CPACR_EL1 access in " Marc Zyngier
2019-07-01 16:40   ` Alexandru Elisei
2019-06-21  9:38 ` [PATCH 21/59] KVM: arm64: nv: Set a handler for the system instruction traps Marc Zyngier
2019-06-25 12:55   ` Julien Thierry
2019-07-03 14:15     ` Marc Zyngier
2019-06-21  9:38 ` [PATCH 22/59] KVM: arm64: nv: Handle PSCI call via smc from the guest Marc Zyngier
2019-06-21  9:38 ` [PATCH 23/59] KVM: arm64: nv: Respect virtual HCR_EL2.TWX setting Marc Zyngier
2019-06-25 14:19   ` Julien Thierry
2019-07-02 12:54     ` Alexandru Elisei
2019-07-03 14:18     ` Marc Zyngier
2019-06-21  9:38 ` [PATCH 24/59] KVM: arm64: nv: Respect virtual CPTR_EL2.TFP setting Marc Zyngier
2019-06-21  9:38 ` [PATCH 25/59] KVM: arm64: nv: Don't expose SVE to nested guests Marc Zyngier
2019-06-21  9:38 ` [PATCH 26/59] KVM: arm64: nv: Respect the virtual HCR_EL2.NV bit setting Marc Zyngier
2019-06-26  5:31   ` Julien Thierry
2019-07-03 16:31     ` Marc Zyngier
2019-06-21  9:38 ` [PATCH 27/59] KVM: arm64: nv: Respect virtual HCR_EL2.TVM and TRVM settings Marc Zyngier
2019-06-26  6:55   ` Julien Thierry
2019-07-04 14:57     ` Marc Zyngier
2019-06-21  9:38 ` [PATCH 28/59] KVM: arm64: nv: Respect the virtual HCR_EL2.NV1 bit setting Marc Zyngier
2019-06-26  7:23   ` Julien Thierry
2019-07-02 16:32   ` Alexandru Elisei
2019-07-03  9:10     ` Alexandru Elisei
2019-06-21  9:38 ` [PATCH 29/59] KVM: arm64: nv: Emulate EL12 register accesses from the virtual EL2 Marc Zyngier
2019-07-03  9:16   ` Alexandru Elisei
2019-06-21  9:38 ` [PATCH 30/59] KVM: arm64: nv: Configure HCR_EL2 for nested virtualization Marc Zyngier
2019-06-21  9:38 ` [PATCH 31/59] KVM: arm64: nv: Only toggle cache for virtual EL2 when SCTLR_EL2 changes Marc Zyngier
2019-06-21  9:38 ` [PATCH 32/59] KVM: arm64: nv: Hide RAS from nested guests Marc Zyngier
2019-07-03 13:59   ` Alexandru Elisei
2019-06-21  9:38 ` [PATCH 33/59] KVM: arm64: nv: Pretend we only support larger-than-host page sizes Marc Zyngier
2019-07-03 14:13   ` Alexandru Elisei
2019-06-21  9:38 ` [PATCH 34/59] KVM: arm/arm64: nv: Factor out stage 2 page table data from struct kvm Marc Zyngier
2019-07-03 15:52   ` Alexandru Elisei
2019-06-21  9:38 ` [PATCH 35/59] KVM: arm/arm64: nv: Support multiple nested stage 2 mmu structures Marc Zyngier
2019-06-25 12:19   ` Alexandru Elisei
2019-07-03 13:47     ` Marc Zyngier
2019-06-27 13:15   ` Julien Thierry
2019-07-04 15:51   ` Alexandru Elisei
2019-06-21  9:38 ` [PATCH 36/59] KVM: arm64: nv: Implement nested Stage-2 page table walk logic Marc Zyngier
2019-06-21  9:38 ` [PATCH 37/59] KVM: arm64: nv: Handle shadow stage 2 page faults Marc Zyngier
2019-07-05 14:28   ` Alexandru Elisei
2019-06-21  9:38 ` [PATCH 38/59] KVM: arm64: nv: Unmap/flush shadow stage 2 page tables Marc Zyngier
2019-07-01  8:03   ` Julien Thierry
2019-06-21  9:38 ` [PATCH 39/59] KVM: arm64: nv: Move last_vcpu_ran to be per s2 mmu Marc Zyngier
2019-07-01  9:10   ` Julien Thierry
2019-07-05 15:28   ` Alexandru Elisei
2019-06-21  9:38 ` [PATCH 40/59] KVM: arm64: nv: Don't always start an S2 MMU search from the beginning Marc Zyngier
2019-07-09  9:59   ` Alexandru Elisei
2019-06-21  9:38 ` [PATCH 41/59] KVM: arm64: nv: Introduce sys_reg_desc.forward_trap Marc Zyngier
2019-06-21  9:38 ` [PATCH 42/59] KVM: arm64: nv: Rework the system instruction emulation framework Marc Zyngier
2019-06-21  9:38 ` [PATCH 43/59] KVM: arm64: nv: Trap and emulate AT instructions from virtual EL2 Marc Zyngier
2019-07-01 15:45   ` Julien Thierry
2019-07-09 13:20   ` Alexandru Elisei
2019-07-18 12:13     ` Tomasz Nowicki
     [not found]       ` <6537c8d2-3bda-788e-8861-b70971a625cb@arm.com>
2019-07-18 12:59         ` Tomasz Nowicki
2019-07-24 10:25   ` Tomasz Nowicki
2019-07-24 12:39     ` Marc Zyngier
2019-07-24 13:56       ` Tomasz Nowicki
2019-06-21  9:38 ` [PATCH 44/59] KVM: arm64: nv: Trap and emulate TLBI " Marc Zyngier
2019-07-02 12:37   ` Julien Thierry
2019-07-10 10:15   ` Alexandru Elisei
2019-06-21  9:38 ` [PATCH 45/59] KVM: arm64: nv: Handle traps for timer _EL02 and _EL2 sysregs accessors Marc Zyngier
2019-06-21  9:38 ` [PATCH 46/59] KVM: arm64: nv: arch_timer: Support hyp timer emulation Marc Zyngier
2019-07-10 16:23   ` Alexandru Elisei
2019-06-21  9:38 ` [PATCH 47/59] KVM: arm64: nv: Propagate CNTVOFF_EL2 to the virtual EL1 timer Marc Zyngier
2019-08-08  9:34   ` Alexandru Elisei
2019-06-21  9:38 ` [PATCH 48/59] KVM: arm64: nv: Load timer before the GIC Marc Zyngier
2019-07-11 13:17   ` Alexandru Elisei
2019-06-21  9:38 ` [PATCH 49/59] KVM: arm64: nv: vgic-v3: Take cpu_if pointer directly instead of vcpu Marc Zyngier
2019-06-21  9:38 ` [PATCH 50/59] KVM: arm64: nv: Nested GICv3 Support Marc Zyngier
2019-07-16 11:41   ` Alexandru Elisei
2019-06-21  9:38 ` [PATCH 51/59] KVM: arm64: nv: vgic: Emulate the HW bit in software Marc Zyngier
2019-06-21  9:38 ` [PATCH 52/59] KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ Marc Zyngier
2019-07-04  7:38   ` Julien Thierry
2019-07-04  9:01     ` Andre Przywara
2019-07-04  9:04       ` Julien Thierry
2019-06-21  9:38 ` [PATCH 53/59] KVM: arm64: nv: Implement maintenance interrupt forwarding Marc Zyngier
2019-07-04  8:06   ` Julien Thierry
2019-07-16 16:35   ` Alexandru Elisei
2019-06-21  9:38 ` [PATCH 54/59] KVM: arm64: nv: Add nested GICv3 tracepoints Marc Zyngier
2019-06-21  9:38 ` [PATCH 55/59] arm64: KVM: nv: Add handling of EL2-specific timer registers Marc Zyngier
2019-07-11 12:35   ` Alexandru Elisei
2019-07-17 10:19   ` Alexandru Elisei
2019-06-21  9:38 ` [PATCH 56/59] arm64: KVM: nv: Honor SCTLR_EL2.SPAN on entering vEL2 Marc Zyngier
2019-06-21  9:38 ` [PATCH 57/59] arm64: KVM: nv: Handle SCTLR_EL2 RES0/RES1 bits Marc Zyngier
2019-06-21  9:38 ` [PATCH 58/59] arm64: KVM: nv: Restrict S2 RD/WR permissions to match the guest's Marc Zyngier
2019-06-21  9:38 ` [PATCH 59/59] arm64: KVM: nv: Allow userspace to request KVM_ARM_VCPU_NESTED_VIRT Marc Zyngier
     [not found] ` <CANW9uyssDm_0ysC_pnvhHRrnsmFZik+3_ENmFz7L2GCmtH09fw@mail.gmail.com>
2019-06-21 11:21   ` [PATCH 00/59] KVM: arm64: ARMv8.3 Nested Virtualization support Marc Zyngier
2019-08-02 10:11 ` Alexandru Elisei
2019-08-02 10:30   ` Andrew Jones
2019-08-09 10:01   ` Alexandru Elisei
2019-08-09 11:44     ` Andrew Jones
2019-08-09 12:00       ` Alexandru Elisei
2019-08-09 13:00         ` Andrew Jones
2019-08-22 11:57     ` Alexandru Elisei
2019-08-22 15:32       ` Alexandru Elisei

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