From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC6DCC10F14 for ; Mon, 8 Apr 2019 17:08:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8D51C20880 for ; Mon, 8 Apr 2019 17:08:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729064AbfDHRIz (ORCPT ); Mon, 8 Apr 2019 13:08:55 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:53483 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728654AbfDHRIz (ORCPT ); Mon, 8 Apr 2019 13:08:55 -0400 Received: from p5492ee6e.dip0.t-ipconnect.de ([84.146.238.110] helo=nanos) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1hDXlK-0003hs-S6; Mon, 08 Apr 2019 19:08:51 +0200 Date: Mon, 8 Apr 2019 19:08:49 +0200 (CEST) From: Thomas Gleixner To: Sebastian Andrzej Siewior cc: linux-kernel@vger.kernel.org, x86@kernel.org, Andy Lutomirski , Paolo Bonzini , =?ISO-8859-2?Q?Radim_Kr=E8m=E1=F8?= , kvm@vger.kernel.org, "Jason A. Donenfeld" , Rik van Riel , Dave Hansen Subject: Re: [PATCH v9 00/27] x86: load FPU registers on return to userland In-Reply-To: <20190403164156.19645-1-bigeasy@linutronix.de> Message-ID: References: <20190403164156.19645-1-bigeasy@linutronix.de> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Wed, 3 Apr 2019, Sebastian Andrzej Siewior wrote: > This is a refurbished series originally started by by Rik van Riel. The > goal is load the FPU registers on return to userland and not on every > context switch. By this optimisation we can: > - avoid loading the registers if the task stays in kernel and does > not return to userland > - make kernel_fpu_begin() cheaper: it only saves the registers on the > first invocation. The second invocation does not need save them again. > > To access the FPU registers in kernel we need: > - disable preemption to avoid that the scheduler switches tasks. By > doing so it would set TIF_NEED_FPU_LOAD and the FPU registers would be > not valid. > - disable BH because the softirq might use kernel_fpu_begin() and then > set TIF_NEED_FPU_LOAD instead loading the FPU registers on completion. So aside of that one hunk in 24/27 which is either wrong or needs some information in the changelog I couldn't find anything disturbing. With that addressed: Reviewed-by: Thomas Gleixner