From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4F96FA3728 for ; Wed, 16 Oct 2019 15:03:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B91D3218DE for ; Wed, 16 Oct 2019 15:03:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393449AbfJPPDb (ORCPT ); Wed, 16 Oct 2019 11:03:31 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:50517 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726299AbfJPPDb (ORCPT ); Wed, 16 Oct 2019 11:03:31 -0400 Received: from [5.158.153.52] (helo=nanos.tec.linutronix.de) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iKkpa-0007KE-6E; Wed, 16 Oct 2019 17:03:18 +0200 Date: Wed, 16 Oct 2019 17:03:17 +0200 (CEST) From: Thomas Gleixner To: David Laight cc: 'Paolo Bonzini' , Xiaoyao Li , Sean Christopherson , Fenghua Yu , Ingo Molnar , Borislav Petkov , H Peter Anvin , Peter Zijlstra , Andrew Morton , Dave Hansen , Radim Krcmar , Ashok Raj , Tony Luck , Dan Williams , Sai Praneeth Prakhya , Ravi V Shankar , linux-kernel , x86 , "kvm@vger.kernel.org" Subject: RE: [PATCH v9 09/17] x86/split_lock: Handle #AC exception for split lock In-Reply-To: <053924e2d08b4744b9fd10337e83ab2d@AcuMS.aculab.com> Message-ID: References: <1560897679-228028-1-git-send-email-fenghua.yu@intel.com> <1560897679-228028-10-git-send-email-fenghua.yu@intel.com> <20190626203637.GC245468@romley-ivt3.sc.intel.com> <20190925180931.GG31852@linux.intel.com> <3ec328dc-2763-9da5-28d6-e28970262c58@redhat.com> <57f40083-9063-5d41-f06d-fa1ae4c78ec6@redhat.com> <3a12810b-1196-b70a-aa2e-9fe17dc7341a@redhat.com> <053924e2d08b4744b9fd10337e83ab2d@AcuMS.aculab.com> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Wed, 16 Oct 2019, David Laight wrote: > For the smt case, can you make #AC enable a property of the process? > Then disable it on the core if either smt process requires it be disabled? That would be feasible if the logic of the TEST_CTRL_MSR would be AND, but it's OR. Thread0 #AC-EN Thread1 #AC-EN #AC enabled on core 0 0 0 1 0 1 0 1 1 1 1 1 So in order to do flips on VMENTER you'd need to IPI the other thread and handle all the interesting corner cases. The 'Rescue SMT' mitigation stuff on top of core scheduling is ugly enough already, but there the state can be transitionally 'unmitigated' while with #AC you run into trouble immediately if the transitional state is ON at the wrong point. Thanks, tglx