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Thu, 10 Dec 2020 17:12:22 +0000 From: Tom Lendacky To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org Cc: Paolo Bonzini , Jim Mattson , Joerg Roedel , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Borislav Petkov , Ingo Molnar , Thomas Gleixner , Brijesh Singh Subject: [PATCH v5 14/34] KVM: SVM: Add support for SEV-ES GHCB MSR protocol function 0x002 Date: Thu, 10 Dec 2020 11:09:49 -0600 Message-Id: X-Mailer: git-send-email 2.28.0 In-Reply-To: References: Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: CH2PR18CA0049.namprd18.prod.outlook.com (2603:10b6:610:55::29) To CY4PR12MB1352.namprd12.prod.outlook.com (2603:10b6:903:3a::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from tlendack-t1.amd.com (165.204.77.1) by CH2PR18CA0049.namprd18.prod.outlook.com (2603:10b6:610:55::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3654.12 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?LatfYD3ovN3MPUyFkxxaUOTsLQkAyF3AY8ftPNTWLopeeWYC1GPnVaiF9Ibj?= =?us-ascii?Q?6kkm0kUgTlCXoeZKwCZaFNsXGUS5H7mIKs9PnXkWQoZWrO3FjySjluXdnSFj?= =?us-ascii?Q?brHmSZZBHqiTBavWsg7Vuq1PesH2bvpF0YznKOmXMNkedIS9mLyPD1yY8Ge8?= =?us-ascii?Q?mhCYVwi0o/Q2iwOcoQ4Py/mhziyRU3GzHEkyw9e5iXmfmLA2W6KHak1mYKao?= =?us-ascii?Q?nGijRAc6CXj2WTNoPGONrOAvZCDy5u6DeOSXvb34AvsSYVtavS8KHrWAFpP7?= =?us-ascii?Q?vACdqf9iVyXeyNHwrSwMak+0iyMwWHh8aUMCCsQrk0B1t9F3YKToze37Lgwd?= =?us-ascii?Q?jXuQQc/Z822ZQQXglFdxuJrKvcVqJpNfgqphKF7+FXhU36+JmJ3A4UIewUeH?= =?us-ascii?Q?cpoTH/E41Xtlp8/hB4IyYGxzlRRoA2f8u1TJ8q23nLtf1ggn5wdzXEpBZpO2?= =?us-ascii?Q?cmGo0mrPmuydps9y47i9BGgI69lzYl0m9yx6Dk7hevsxWzQrVXWp+JFDq+Ka?= =?us-ascii?Q?74S5fnnhaEx6LZxeJKTO0N0StgyOGbynvqgmIMuPXTNBKVoJ97TwehtrJTeY?= =?us-ascii?Q?xBdB1HbGW87hPgUrgUOS18CmHwD8pQpTTaRByq/2PJoNW4h3uDQyI4Njs9d6?= =?us-ascii?Q?I1/J/xTo9lDle7cCtd3C45OeFnxT9jPafWbzEIAM9F6iQOdqzgdkHMVDsnvb?= =?us-ascii?Q?DbUBoV5jqFfjiZ2vdnyElcs7bISFQHJVRHYZzLsbhNEsqjTjpuJxeTaNXgWo?= =?us-ascii?Q?83kFC5Pr8Xt722K9uuZx9qG/wlSRT0rKjXO2LhVqAmaDPhAGoMZafkbEeFuQ?= =?us-ascii?Q?7a0bNIGTtW0lcmLNSPxbx69oiFiPrMzvLPNWqNvcEwAjtB88FFsw80K1WA9z?= =?us-ascii?Q?kazmcr4bTTD3l5zWOAxkehA33B20BSbqJ9dJd8xR9QyYNmtpHD75eU78MxJN?= =?us-ascii?Q?sjRXIVSxMn64l1x40TbcB3LF3eZEkfT3/4Z0erdon3Ud54heVosgBb4GGdmD?= =?us-ascii?Q?NKmu?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthSource: CY4PR12MB1352.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2020 17:12:22.1309 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-Network-Message-Id: 07837e1c-c515-43de-74b2-08d89d2ec20e X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: agQAVBtkRxbqLMxHmHnalu21QDjnOfTHBHSiWjpMLyODDA8q+ER5yyQU0U9lCSjXibNwj/paFRqpNhQ/pjrtWQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1201MB0168 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Tom Lendacky The GHCB specification defines a GHCB MSR protocol using the lower 12-bits of the GHCB MSR (in the hypervisor this corresponds to the GHCB GPA field in the VMCB). Function 0x002 is a request to set the GHCB MSR value to the SEV INFO as per the specification via the VMCB GHCB GPA field. Signed-off-by: Tom Lendacky --- arch/x86/kvm/svm/sev.c | 26 +++++++++++++++++++++++++- arch/x86/kvm/svm/svm.h | 17 +++++++++++++++++ 2 files changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index da473c6b725e..58861515d3e3 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -22,6 +22,7 @@ #include "cpuid.h" #include "trace.h" +static u8 sev_enc_bit; static int sev_flush_asids(void); static DECLARE_RWSEM(sev_deactivate_lock); static DEFINE_MUTEX(sev_bitmap_lock); @@ -1142,6 +1143,9 @@ void __init sev_hardware_setup(void) /* Retrieve SEV CPUID information */ cpuid(0x8000001f, &eax, &ebx, &ecx, &edx); + /* Set encryption bit location for SEV-ES guests */ + sev_enc_bit = ebx & 0x3f; + /* Maximum number of encrypted guests supported simultaneously */ max_sev_asid = ecx; @@ -1500,9 +1504,29 @@ void pre_sev_run(struct vcpu_svm *svm, int cpu) vmcb_mark_dirty(svm->vmcb, VMCB_ASID); } +static void set_ghcb_msr(struct vcpu_svm *svm, u64 value) +{ + svm->vmcb->control.ghcb_gpa = value; +} + static int sev_handle_vmgexit_msr_protocol(struct vcpu_svm *svm) { - return -EINVAL; + struct vmcb_control_area *control = &svm->vmcb->control; + u64 ghcb_info; + + ghcb_info = control->ghcb_gpa & GHCB_MSR_INFO_MASK; + + switch (ghcb_info) { + case GHCB_MSR_SEV_INFO_REQ: + set_ghcb_msr(svm, GHCB_MSR_SEV_INFO(GHCB_VERSION_MAX, + GHCB_VERSION_MIN, + sev_enc_bit)); + break; + default: + return -EINVAL; + } + + return 1; } int sev_handle_vmgexit(struct vcpu_svm *svm) diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 89bcb26977e5..546f8d05e81e 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -514,9 +514,26 @@ void svm_vcpu_unblocking(struct kvm_vcpu *vcpu); /* sev.c */ +#define GHCB_VERSION_MAX 1ULL +#define GHCB_VERSION_MIN 1ULL + #define GHCB_MSR_INFO_POS 0 #define GHCB_MSR_INFO_MASK (BIT_ULL(12) - 1) +#define GHCB_MSR_SEV_INFO_RESP 0x001 +#define GHCB_MSR_SEV_INFO_REQ 0x002 +#define GHCB_MSR_VER_MAX_POS 48 +#define GHCB_MSR_VER_MAX_MASK 0xffff +#define GHCB_MSR_VER_MIN_POS 32 +#define GHCB_MSR_VER_MIN_MASK 0xffff +#define GHCB_MSR_CBIT_POS 24 +#define GHCB_MSR_CBIT_MASK 0xff +#define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \ + ((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) | \ + (((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) | \ + (((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) | \ + GHCB_MSR_SEV_INFO_RESP) + extern unsigned int max_sev_asid; static inline bool svm_sev_enabled(void) -- 2.28.0