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From: "Gupta, Pankaj" <pankaj.gupta@amd.com>
To: Tianyu Lan <ltykernel@gmail.com>,
	luto@kernel.org, tglx@linutronix.de, mingo@redhat.com,
	bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org,
	hpa@zytor.com, seanjc@google.com, pbonzini@redhat.com,
	jgross@suse.com, tiala@microsoft.com, kirill@shutemov.name,
	jiangshan.ljs@antgroup.com, peterz@infradead.org,
	ashish.kalra@amd.com, srutherford@google.com,
	akpm@linux-foundation.org, anshuman.khandual@arm.com,
	pawan.kumar.gupta@linux.intel.com, adrian.hunter@intel.com,
	daniel.sneddon@linux.intel.com,
	alexander.shishkin@linux.intel.com, sandipan.das@amd.com,
	ray.huang@amd.com, brijesh.singh@amd.com, michael.roth@amd.com,
	thomas.lendacky@amd.com, venu.busireddy@oracle.com,
	sterritt@google.com, tony.luck@intel.com,
	samitolvanen@google.com, fenghua.yu@intel.com
Cc: pangupta@amd.com, linux-kernel@vger.kernel.org,
	kvm@vger.kernel.org, linux-hyperv@vger.kernel.org,
	linux-arch@vger.kernel.org
Subject: Re: [RFC PATCH V5 11/15] x86/sev: Add a #HV exception handler
Date: Thu, 11 May 2023 15:25:55 +0200	[thread overview]
Message-ID: <c40fdde7-52d6-c50f-03f4-58584f11ba4d@amd.com> (raw)
In-Reply-To: <3ec60d7a-c5e7-2570-a0f2-ef435d904cfd@amd.com>

On 5/5/2023 12:59 PM, Gupta, Pankaj wrote:
> Hi Tianyu,
> 
> I tried to understand some details of this patch. Please find below
> some comments/questions.
> 
> Thanks,
> 
> 
>> Add a #HV exception handler that uses IST stack.
>>
>> Signed-off-by: Tianyu Lan <tiala@microsoft.com>
>> ---
>> Change since RFC V2:
>>         * Remove unnecessary line in the change log.
>> ---
>>   arch/x86/entry/entry_64.S             | 22 +++++++----
>>   arch/x86/include/asm/cpu_entry_area.h |  6 +++
>>   arch/x86/include/asm/idtentry.h       | 40 +++++++++++++++++++-
>>   arch/x86/include/asm/page_64_types.h  |  1 +
>>   arch/x86/include/asm/trapnr.h         |  1 +
>>   arch/x86/include/asm/traps.h          |  1 +
>>   arch/x86/kernel/cpu/common.c          |  1 +
>>   arch/x86/kernel/dumpstack_64.c        |  9 ++++-
>>   arch/x86/kernel/idt.c                 |  1 +
>>   arch/x86/kernel/sev.c                 | 53 +++++++++++++++++++++++++++
>>   arch/x86/kernel/traps.c               | 40 ++++++++++++++++++++
>>   arch/x86/mm/cpu_entry_area.c          |  2 +
>>   12 files changed, 165 insertions(+), 12 deletions(-)
>>
>> diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S
>> index eccc3431e515..653b1f10699b 100644
>> --- a/arch/x86/entry/entry_64.S
>> +++ b/arch/x86/entry/entry_64.S
>> @@ -496,7 +496,7 @@ SYM_CODE_END(\asmsym)
>>   #ifdef CONFIG_AMD_MEM_ENCRYPT
>>   /**
>> - * idtentry_vc - Macro to generate entry stub for #VC
>> + * idtentry_sev - Macro to generate entry stub for #VC
>>    * @vector:        Vector number
>>    * @asmsym:        ASM symbol for the entry point
>>    * @cfunc:        C function to be called
>> @@ -515,14 +515,18 @@ SYM_CODE_END(\asmsym)
>>    *
>>    * The macro is only used for one vector, but it is planned to be 
>> extended in
>>    * the future for the #HV exception.
>> - */
>> -.macro idtentry_vc vector asmsym cfunc
>> +*/
>> +.macro idtentry_sev vector asmsym cfunc has_error_code:req
>>   SYM_CODE_START(\asmsym)
>>       UNWIND_HINT_IRET_REGS
>>       ENDBR
>>       ASM_CLAC
>>       cld
>> +    .if \vector == X86_TRAP_HV
>> +        pushq    $-1            /* ORIG_RAX: no syscall */
>> +    .endif
>> +
>>       /*
>>        * If the entry is from userspace, switch stacks and treat it as
>>        * a normal entry.
>> @@ -545,7 +549,12 @@ SYM_CODE_START(\asmsym)
>>        * stack.
>>        */
>>       movq    %rsp, %rdi        /* pt_regs pointer */
>> -    call    vc_switch_off_ist
>> +    .if \vector == X86_TRAP_VC
>> +        call    vc_switch_off_ist
> 
> I think the stack switching logic is similar for #VC & #HV.
> So, we can use common function. Just the corresponding fallback
> stack switching is different. Maybe we can pass the hint as an
> argument (%rsi?) to something like "sev_switch_off_ist()", and use
> the corresponding (#HV or #VC) fallbacks stack?

Also, Please include the below patch from Ashish for #HV
reentrancy check.

https://github.com/ashkalra/linux/commit/6975484094b7cb8d703c45066780dd85043cd040

Thanks,
Pankaj


  reply	other threads:[~2023-05-11 13:28 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-01  8:57 [RFC PATCH V5 00/15] x86/hyperv/sev: Add AMD sev-snp enlightened guest support on hyperv Tianyu Lan
2023-05-01  8:57 ` [RFC PATCH V5 01/15] x86/hyperv: Add sev-snp enlightened guest static key Tianyu Lan
2023-05-01  8:57 ` [RFC PATCH V5 02/15] x86/hyperv: Decrypt hv vp assist page in sev-snp enlightened guest Tianyu Lan
2023-05-01 15:10   ` Tom Lendacky
2023-05-01  8:57 ` [RFC PATCH V5 03/15] x86/hyperv: Set Virtual Trust Level in VMBus init message Tianyu Lan
2023-05-02 19:30   ` Zhi Wang
2023-05-04 15:38     ` Tianyu Lan
2023-05-04 15:58       ` Zhi Wang
2023-05-01  8:57 ` [RFC PATCH V5 04/15] x86/hyperv: Use vmmcall to implement Hyper-V hypercall in sev-snp enlightened guest Tianyu Lan
2023-05-01  8:57 ` [RFC PATCH V5 05/15] clocksource/drivers/hyper-v: decrypt hyperv tsc page " Tianyu Lan
2023-05-04 16:54   ` Zhi Wang
2023-05-01  8:57 ` [RFC PATCH V5 06/15] hv: vmbus: decrypt VMBus pages for " Tianyu Lan
2023-05-01  8:57 ` [RFC PATCH V5 07/15] drivers: hv: Decrypt percpu hvcall input arg page in " Tianyu Lan
2023-05-01  8:57 ` [RFC PATCH V5 08/15] x86/hyperv: Initialize cpu and memory for " Tianyu Lan
2023-05-01  8:57 ` [RFC PATCH V5 09/15] x86/hyperv: Add smp support for sev-snp guest Tianyu Lan
2023-05-01 10:20   ` [EXTERNAL] " Saurabh Singh Sengar
2023-05-04 15:55     ` Tianyu Lan
2023-05-01 10:32   ` Saurabh Singh Sengar
2023-05-01 15:46   ` Tom Lendacky
2023-05-04 15:51     ` Tianyu Lan
2023-05-01  8:57 ` [RFC PATCH V5 10/15] x86/hyperv: Add hyperv-specific handling for VMMCALL under SEV-ES Tianyu Lan
2023-05-01  8:57 ` [RFC PATCH V5 11/15] x86/sev: Add a #HV exception handler Tianyu Lan
2023-05-05 10:59   ` Gupta, Pankaj
2023-05-11 13:25     ` Gupta, Pankaj [this message]
2023-05-01  8:57 ` [RFC PATCH V5 12/15] x86/sev: Add Check of #HV event in path Tianyu Lan
2023-05-01  8:57 ` [RFC PATCH V5 13/15] x86/sev: Add AMD sev-snp enlightened guest support on hyperv Tianyu Lan
2023-05-01  8:57 ` [RFC PATCH V5 14/15] x86/sev: optimize system vector processing invoked from #HV exception Tianyu Lan
2023-05-01  8:57 ` [RFC PATCH V5 15/15] x86/sev: Fix interrupt exit code paths " Tianyu Lan
2023-05-01 16:02   ` Tom Lendacky
2023-05-04 22:41     ` Tianyu Lan
2023-05-01 16:05 ` [RFC PATCH V5 00/15] x86/hyperv/sev: Add AMD sev-snp enlightened guest support on hyperv Tom Lendacky

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