From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E788C3A5A9 for ; Sat, 2 May 2020 22:21:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 835C72137B for ; Sat, 2 May 2020 22:21:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728558AbgEBWVr convert rfc822-to-8bit (ORCPT ); Sat, 2 May 2020 18:21:47 -0400 Received: from lhrrgout.huawei.com ([185.176.76.210]:2147 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728530AbgEBWVr (ORCPT ); Sat, 2 May 2020 18:21:47 -0400 Received: from lhreml714-chm.china.huawei.com (unknown [172.18.7.108]) by Forcepoint Email with ESMTP id 2AF87D59739CFA60A635; Sat, 2 May 2020 23:21:45 +0100 (IST) Received: from dggeme755-chm.china.huawei.com (10.3.19.101) by lhreml714-chm.china.huawei.com (10.201.108.65) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1913.5; Sat, 2 May 2020 23:21:43 +0100 Received: from dggeme755-chm.china.huawei.com ([10.7.64.71]) by dggeme755-chm.china.huawei.com ([10.7.64.71]) with mapi id 15.01.1913.007; Sun, 3 May 2020 06:21:41 +0800 From: gengdongjiu To: Igor Mammedov CC: Peter Maydell , Fam Zheng , "Xiao Guangrong" , kvm-devel , "Michael S. Tsirkin" , Marcelo Tosatti , QEMU Developers , Eduardo Habkost , Linuxarm , Shannon Zhao , "zhengxiang (A)" , qemu-arm , Jonathan Cameron , Paolo Bonzini , "Richard Henderson" Subject: Re: [PATCH v25 00/10] Add ARMv8 RAS virtualization support in QEMU Thread-Topic: [PATCH v25 00/10] Add ARMv8 RAS virtualization support in QEMU Thread-Index: AdYgz//oho/0lGTqbEC6pfKPUDNKmA== Date: Sat, 2 May 2020 22:21:41 +0000 Message-ID: Accept-Language: zh-CN, en-US Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.46.14.22] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-CFilter-Loop: Reflected Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org > > On Thu, 30 Apr 2020 11:56:24 +0800 > gengdongjiu wrote: > > > On 2020/4/17 21:32, Peter Maydell wrote: > > > On Fri, 10 Apr 2020 at 12:46, Dongjiu Geng wrote: > > >> > > >> In the ARMv8 platform, the CPU error types includes synchronous > > >> external abort(SEA) and SError Interrupt (SEI). If exception > > >> happens in guest, host does not know the detailed information of > > >> guest, so it is expected that guest can do the recovery. For > > >> example, if an exception happens in a guest user-space application, host does not know which application encounters errors, only > guest knows it. > > >> > > >> For the ARMv8 SEA/SEI, KVM or host kernel delivers SIGBUS to notify userspace. > > >> After user space gets the notification, it will record the CPER > > >> into guest GHES buffer and inject an exception or IRQ to guest. > > >> > > >> In the current implementation, if the type of SIGBUS is > > >> BUS_MCEERR_AR, we will treat it as a synchronous exception, and > > >> notify guest with ARMv8 SEA notification type after recording CPER into guest. > > > > > > Hi. I left a comment on patch 1. The other 3 patches unreviewed are > > > 5, 6 and 8, which are all ACPI core code, so that's for MST, Igor or > > > Shannon to review. > > > > Ping MST, Igor and Shannon, sorry for the noise. > > I put it on my review queue Igor, thank you very much in advance. > > > > > > > > > Once those have been reviewed, please ping me if you want this to go > > > via target-arm.next. > > > > > > thanks > > > -- PMM > > > > > > . > > > > >