From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47175C76192 for ; Wed, 17 Jul 2019 01:17:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 29F5820665 for ; Wed, 17 Jul 2019 01:17:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725899AbfGQBRb (ORCPT ); Tue, 16 Jul 2019 21:17:31 -0400 Received: from mga09.intel.com ([134.134.136.24]:48554 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725850AbfGQBRb (ORCPT ); Tue, 16 Jul 2019 21:17:31 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Jul 2019 18:17:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,272,1559545200"; d="scan'208";a="366853507" Received: from txu2-mobl.ccr.corp.intel.com (HELO [10.239.196.165]) ([10.239.196.165]) by fmsmga006.fm.intel.com with ESMTP; 16 Jul 2019 18:17:28 -0700 Subject: Re: [PATCH v7 2/3] KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL To: Eduardo Habkost Cc: pbonzini@redhat.com, rkrcmar@redhat.com, corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, sean.j.christopherson@intel.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, fenghua.yu@intel.com, xiaoyao.li@linux.intel.com, jingqi.liu@intel.com References: <20190712082907.29137-1-tao3.xu@intel.com> <20190712082907.29137-3-tao3.xu@intel.com> <20190716160358.GE26800@habkost.net> From: Tao Xu Message-ID: Date: Wed, 17 Jul 2019 09:17:27 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190716160358.GE26800@habkost.net> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Archived-At: List-Archive: List-Post: On 7/17/2019 12:03 AM, Eduardo Habkost wrote: > On Fri, Jul 12, 2019 at 04:29:06PM +0800, Tao Xu wrote: >> UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H >> to determines the maximum time in TSC-quanta that the processor can reside >> in either C0.1 or C0.2. >> >> This patch emulates MSR IA32_UMWAIT_CONTROL in guest and differentiate >> IA32_UMWAIT_CONTROL between host and guest. The variable >> mwait_control_cached in arch/x86/power/umwait.c caches the MSR value, so >> this patch uses it to avoid frequently rdmsr of IA32_UMWAIT_CONTROL. >> >> Co-developed-by: Jingqi Liu >> Signed-off-by: Jingqi Liu >> Signed-off-by: Tao Xu >> --- > [...] >> +static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx) >> +{ >> + if (!vmx_has_waitpkg(vmx)) >> + return; >> + >> + if (vmx->msr_ia32_umwait_control != umwait_control_cached) >> + add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL, >> + vmx->msr_ia32_umwait_control, >> + umwait_control_cached, false); > > How exactly do we ensure NR_AUTOLOAD_MSRS (8) is still large enough? > > I see 3 existing add_atomic_switch_msr() calls, but the one at > atomic_switch_perf_msrs() is in a loop. Are we absolutely sure > that perf_guest_get_msrs() will never return more than 5 MSRs? > Quote the code of intel_guest_get_msrs: static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) { [...] arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask; arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask; if (x86_pmu.flags & PMU_FL_PEBS_ALL) arr[0].guest &= ~cpuc->pebs_enabled; else arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); *nr = 1; if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) { [...] arr[1].msr = MSR_IA32_PEBS_ENABLE; arr[1].host = cpuc->pebs_enabled; arr[1].guest = 0; *nr = 2; [...] There are most 2 msrs now. By default umwait is disabled in KVM. So by default there is no MSR_IA32_UMWAIT_CONTROL added into add_atomic_switch_msr(). Thanks. > >> + else >> + clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL); >> +} >> + >> static void vmx_arm_hv_timer(struct vcpu_vmx *vmx, u32 val) >> { >> vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, val); > [...] > >