From 24a04b800d24e3b493e5094f88649402923147a2 Mon Sep 17 00:00:00 2001 From: Like Xu Date: Fri, 4 Sep 2020 10:19:27 +0800 Subject: [PATCH 1/2] target/i386: Expose PEBS capabilities in the FEAT_PERF_CAPABILITIES The IA32_PERF_CAPABILITIES MSR provides enumeration of a variety of PEBS feature interfaces: - PEBSTrap[6]: Trap/Fault-like indicator of PEBS recording assist; - PEBSArchRegs[7]: Indicator of PEBS assist save architectural registers; - PEBS_FMT[bits 11:8]: Specifies the encoding of the layout of PEBS records; - PEBS_BASELINE [bit 14]: If set, the following is true: (1) Extended PEBS is supported. All counters support the PEBS facility, and all events can generate PEBS records when PEBS is enabled. (2) Adaptive PEBS is supported. The PEBS_DATA_CFG MSR and adaptive record enable bits are supported. Signed-off-by: Like Xu --- target/i386/cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 72a79e6019..14262c7bf7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1136,9 +1136,9 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .type = MSR_FEATURE_WORD, .feat_names = { NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, "full-width-write", NULL, NULL, + NULL, NULL, "pebs-trap", "pebs-arch-reg", + "pebs-fmt-0", "pebs-fmt-1", "pebs-fmt-2", "pebs-fmt-3", + NULL, "full-width-write", "pebs-baseline", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, -- 2.29.2