From be5246694aaf2132396ee0b907e679f5c9ccd089 Mon Sep 17 00:00:00 2001 From: Like Xu Date: Fri, 4 Sep 2020 10:42:28 +0800 Subject: [PATCH 2/2] target/i386: add -cpu,pebs=true support to enable guest PEBS The PEBS feature would be enabled on the guest if: - the KVM is enabled and the PMU is enabled and, - the msr-based-feature IA32_PERF_CAPABILITIES is supporterd and, - the supported returned value for PEBS from this msr is not zero. The PEBS feature would be disabled on the guest if: - the msr-based-feature IA32_PERF_CAPABILITIES is unsupporterd OR, - qemu set the IA32_PERF_CAPABILITIES msr feature without pebs_fmt values OR, - the requested guest vcpu model doesn't support PDCM. Signed-off-by: Like Xu --- hw/i386/pc.c | 1 + target/i386/cpu.c | 20 ++++++++++++++++++++ target/i386/cpu.h | 7 +++++++ target/i386/kvm/kvm.c | 10 ++++++++++ 4 files changed, 38 insertions(+) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 5458f61d10..8e9c1b7545 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -330,6 +330,7 @@ GlobalProperty pc_compat_1_5[] = { { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, { "virtio-net-pci", "any_layout", "off" }, { TYPE_X86_CPU, "pmu", "on" }, + { TYPE_X86_CPU, "pebs", "on" }, { "i440FX-pcihost", "short_root_bus", "0" }, { "q35-pcihost", "short_root_bus", "0" }, }; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 14262c7bf7..9dffc85542 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4228,6 +4228,12 @@ static bool lmce_supported(void) return !!(mce_cap & MCG_LMCE_P); } +static inline bool lbr_supported(void) +{ + return kvm_enabled() && (kvm_arch_get_supported_msr_feature(kvm_state, + MSR_IA32_PERF_CAPABILITIES) & PERF_CAP_PEBS_FORMAT); +} + #define CPUID_MODEL_ID_SZ 48 /** @@ -4332,6 +4338,9 @@ static void max_x86_cpu_initfn(Object *obj) } object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); + if (lbr_supported()) { + object_property_set_bool(OBJECT(cpu), "pebs", true, &error_abort); + } } static const TypeInfo max_x86_cpu_type_info = { @@ -5545,6 +5554,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, } if (!cpu->enable_pmu) { *ecx &= ~CPUID_EXT_PDCM; + if (cpu->enable_pebs) { + warn_report("PEBS is unsupported since guest PMU is disabled."); + exit(1); + } } break; case 2: @@ -6610,6 +6623,12 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) } } + if (!cpu->max_features && cpu->enable_pebs && + !(env->features[FEAT_1_ECX] & CPUID_EXT_PDCM)) { + warn_report("requested vcpu model doesn't support PDCM for PEBS."); + exit(1); + } + if (cpu->ucode_rev == 0) { /* The default is the same as KVM's. */ if (IS_AMD_CPU(env)) { @@ -7192,6 +7211,7 @@ static Property x86_cpu_properties[] = { #endif DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), + DEFINE_PROP_BOOL("pebs", X86CPU, enable_pebs, false), DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, HYPERV_SPINLOCK_NEVER_NOTIFY), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d23a5b340a..eac8d8c68e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -354,6 +354,12 @@ typedef enum X86Seg { #define ARCH_CAP_TSX_CTRL_MSR (1<<7) #define MSR_IA32_PERF_CAPABILITIES 0x345 +#define PERF_CAP_PEBS_TRAP BIT_ULL(6) +#define PERF_CAP_ARCH_REG BIT_ULL(7) +#define PERF_CAP_PEBS_FORMAT 0xf00 +#define PERF_CAP_PEBS_BASELINE BIT_ULL(14) +#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ + PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE) #define MSR_IA32_TSX_CTRL 0x122 #define MSR_IA32_TSCDEADLINE 0x6e0 @@ -1708,6 +1714,7 @@ struct X86CPU { * capabilities) directly to the guest. */ bool enable_pmu; + bool enable_pebs; /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is * disabled by default to avoid breaking migration between QEMU with diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 6dc1ee052d..8fe1d2feea 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2705,6 +2705,13 @@ static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f) MSR_IA32_PERF_CAPABILITIES); if (kvm_perf_cap) { + if (!cpu->enable_pebs) { + kvm_perf_cap &= ~PERF_CAP_PEBS_MASK; + } + if (!(kvm_perf_cap & PERF_CAP_PEBS_MASK) && cpu->enable_pebs) { + warn_report("MSR_IA32_PERF_CAPABILITIES reported by KVM does not support PEBS."); + exit(1); + } kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES, kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]); } @@ -2744,6 +2751,9 @@ static void kvm_init_msrs(X86CPU *cpu) if (has_msr_perf_capabs && cpu->enable_pmu) { kvm_msr_entry_add_perf(cpu, env->features); + } else if (!has_msr_perf_capabs && cpu->enable_pebs) { + warn_report("KVM doesn't support MSR_IA32_PERF_CAPABILITIES for PEBS."); + exit(1); } if (has_msr_ucode_rev) { -- 2.29.2