From: Like Xu <like.xu.linux@gmail.com>
To: Yang Weijiang <weijiang.yang@intel.com>
Cc: pbonzini@redhat.com, jmattson@google.com, seanjc@google.com,
vkuznets@redhat.com, wei.w.wang@intel.com, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v7 13/15] KVM: x86/vmx: Clear Arch LBREn bit before inject #DB to guest
Date: Mon, 9 Aug 2021 13:08:32 +0800 [thread overview]
Message-ID: <fde88a8a-fd9b-b192-caae-105224d78b47@gmail.com> (raw)
In-Reply-To: <1628235745-26566-14-git-send-email-weijiang.yang@intel.com>
On 6/8/2021 3:42 pm, Yang Weijiang wrote:
> Per ISA spec, need to clear the bit before inject #DB.
Please paste the SDM statement accurately so that the reviewers
can verify that the code is consistent with the documentation.
>
> Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
> ---
> arch/x86/kvm/vmx/vmx.c | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> index 70314cd93340..31b9c06c9b3b 100644
> --- a/arch/x86/kvm/vmx/vmx.c
> +++ b/arch/x86/kvm/vmx/vmx.c
> @@ -1601,6 +1601,21 @@ static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
> vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
> }
>
> +static void flip_arch_lbr_ctl(struct kvm_vcpu *vcpu, bool on)
> +{
> + if (vcpu_to_pmu(vcpu)->event_count > 0 &&
Ugh, this check seems ridiculous/funny to me.
> + kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR)) {
> + u64 lbr_ctl = vmcs_read64(GUEST_IA32_LBR_CTL);
> +
> + if (on)
> + lbr_ctl |= 1ULL;
> + else
> + lbr_ctl &= ~1ULL;
> +
> + vmcs_write64(GUEST_IA32_LBR_CTL, lbr_ctl);
> + }
> +}
...
next prev parent reply other threads:[~2021-08-09 5:08 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-06 7:42 [PATCH v7 00/15] Introduce Architectural LBR for vPMU Yang Weijiang
2021-08-06 7:42 ` [PATCH v7 01/15] perf/x86/intel: Fix the comment about guest LBR support on KVM Yang Weijiang
2021-08-06 7:42 ` [PATCH v7 02/15] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers Yang Weijiang
2021-08-06 7:42 ` [PATCH v7 03/15] KVM: x86: Add Arch LBR MSRs to msrs_to_save_all list Yang Weijiang
2021-08-09 13:07 ` Like Xu
2021-08-06 7:42 ` [PATCH v7 04/15] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for guest Arch LBR Yang Weijiang
2021-08-09 13:16 ` Like Xu
2021-08-10 7:38 ` Yang Weijiang
2021-08-10 7:54 ` Like Xu
2021-08-10 9:08 ` Yang Weijiang
2021-08-06 7:42 ` [PATCH v7 05/15] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL " Yang Weijiang
2021-08-06 16:26 ` kernel test robot
2021-08-09 13:36 ` Like Xu
2021-08-10 8:30 ` Yang Weijiang
2021-08-10 8:37 ` Like Xu
2021-08-06 7:42 ` [PATCH v7 06/15] KVM: x86/pmu: Refactor code to support " Yang Weijiang
2021-08-06 7:42 ` [PATCH v7 07/15] KVM: x86: Refresh CPUID on writes to MSR_IA32_XSS Yang Weijiang
2021-08-06 7:42 ` [PATCH v7 08/15] KVM: x86: Report XSS as an MSR to be saved if there are supported features Yang Weijiang
2021-08-06 7:42 ` [PATCH v7 09/15] KVM: x86: Refine the matching and clearing logic for supported_xss Yang Weijiang
2021-08-06 7:42 ` [PATCH v7 10/15] KVM: x86: Add XSAVE Support for Architectural LBR Yang Weijiang
2021-08-06 7:42 ` [PATCH v7 11/15] KVM: x86/vmx: Check Arch LBR config when return perf capabilities Yang Weijiang
2021-08-06 7:42 ` [PATCH v7 12/15] KVM: nVMX: Add necessary Arch LBR settings for nested VM Yang Weijiang
2021-08-06 7:42 ` [PATCH v7 13/15] KVM: x86/vmx: Clear Arch LBREn bit before inject #DB to guest Yang Weijiang
2021-08-09 5:08 ` Like Xu [this message]
2021-08-09 9:02 ` Yang Weijiang
2021-08-06 7:42 ` [PATCH v7 14/15] KVM: x86/vmx: Flip Arch LBREn bit on guest state change Yang Weijiang
2021-08-06 7:42 ` [PATCH v7 15/15] KVM: x86/cpuid: Advise Arch LBR feature in CPUID Yang Weijiang
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