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From: Andrew Murray <andrew.murray@arm.com>
To: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>
Cc: Andrew Murray <andrew.murray@arm.com>,
	kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 2/3] KVM: arm64: limit PMU version to PMUv3 for ARMv8.1
Date: Mon, 27 Jan 2020 11:44:28 +0000
Message-ID: <1580125469-23887-3-git-send-email-andrew.murray@arm.com> (raw)
In-Reply-To: <1580125469-23887-1-git-send-email-andrew.murray@arm.com>

We currently expose the PMU version of the host to the guest via
emulation of the DFR0_EL1 and AA64DFR0_EL1 debug feature registers.
However many of the features offered beyond PMUv3 for 8.1 are not
supported in KVM. Examples of this include support for the PMMIR
registers (added in PMUv3 for ARMv8.4) and 64-bit event counters
added in (PMUv3 for ARMv8.5).

Let's trap the Debug Feature Registers in order to limit
PMUVer/PerfMon in the Debug Feature Registers to PMUv3 for ARMv8.1
to avoid unexpected behaviour.

Signed-off-by: Andrew Murray <andrew.murray@arm.com>
---
 arch/arm64/include/asm/sysreg.h |  5 +++++
 arch/arm64/kvm/sys_regs.c       | 11 +++++++++++
 2 files changed, 16 insertions(+)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 6e919fa..1009878 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -672,6 +672,11 @@
 #define ID_AA64DFR0_TRACEVER_SHIFT	4
 #define ID_AA64DFR0_DEBUGVER_SHIFT	0
 
+#define ID_DFR0_PERFMON_SHIFT		24
+
+#define ID_DFR0_EL1_PMUVER_8_1		4
+#define ID_AA64DFR0_EL1_PMUVER_8_1	4
+
 #define ID_ISAR5_RDM_SHIFT		24
 #define ID_ISAR5_CRC32_SHIFT		16
 #define ID_ISAR5_SHA2_SHIFT		12
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 9f21659..3f0f3cc 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1085,6 +1085,17 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
 			 (0xfUL << ID_AA64ISAR1_API_SHIFT) |
 			 (0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
 			 (0xfUL << ID_AA64ISAR1_GPI_SHIFT));
+	} else if (id == SYS_ID_AA64DFR0_EL1) {
+		/* Limit guests to PMUv3 for ARMv8.1 */
+		val = cpuid_feature_cap_signed_field_width(val,
+						ID_AA64DFR0_PMUVER_SHIFT,
+						4, ID_AA64DFR0_EL1_PMUVER_8_1);
+	} else if (id == SYS_ID_DFR0_EL1) {
+		/* Limit guests to PMUv3 for ARMv8.1 */
+		val = cpuid_feature_cap_signed_field_width(val,
+						ID_DFR0_PERFMON_SHIFT,
+						4, ID_DFR0_EL1_PMUVER_8_1);
+
 	}
 
 	return val;
-- 
2.7.4

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  parent reply index

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-27 11:44 [PATCH v5 0/3] arm64: perf: Add support for ARMv8.5-PMU 64-bit counters Andrew Murray
2020-01-27 11:44 ` [PATCH v5 1/3] arm64: cpufeature: Extract capped fields Andrew Murray
2020-02-11 16:59   ` Suzuki Kuruppassery Poulose
2020-01-27 11:44 ` Andrew Murray [this message]
2020-02-11 17:55   ` [PATCH v5 2/3] KVM: arm64: limit PMU version to PMUv3 for ARMv8.1 Suzuki Kuruppassery Poulose
2020-02-28 16:51   ` Mark Rutland
2020-02-28 18:22     ` Mark Rutland
2020-01-27 11:44 ` [PATCH v5 3/3] arm64: perf: Add support for ARMv8.5-PMU 64-bit counters Andrew Murray
2020-01-27 12:32   ` Marc Zyngier
2020-01-28  8:53     ` Andrew Murray

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