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From: Marc Zyngier <marc.zyngier@arm.com>
To: James Morse <james.morse@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	kvmarm@lists.cs.columbia.edu
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will.deacon@arm.com>
Subject: Re: [PATCH v2] KVM: arm64: Skip more of the SError vaxorcism
Date: Mon, 10 Jun 2019 17:58:10 +0100
Message-ID: <1d806015-bbad-c2dd-2ff6-2a5bdb73e117@arm.com> (raw)
In-Reply-To: <20190610163034.116151-1-james.morse@arm.com>

Hi James,

On 10/06/2019 17:30, James Morse wrote:
> During __guest_exit() we need to consume any SError left pending by the
> guest so it doesn't contaminate the host. With v8.2 we use the
> ESB-instruction. For systems without v8.2, we use dsb+isb and unmask
> SError. We do this on every guest exit.
> 
> Use the same dsb+isr_el1 trick, this lets us know if an SError is pending
> after the dsb, allowing us to skip the isb and self-synchronising PSTATE
> write if its not.
> 
> This means SError remains masked during KVM's world-switch, so any SError
> that occurs during this time is reported by the host, instead of causing
> a hyp-panic.

Ah, that'd be pretty good.

> 
> If you give gcc likely()/unlikely() hints in an if() condition, it
> shuffles the generated assembly so that the likely case is immediately
> after the branch. Lets do the same here.
> 
> Signed-off-by: James Morse <james.morse@arm.com>
> ---
> This patch was previously posted as part of:
> [v1] https://lore.kernel.org/linux-arm-kernel/20190604144551.188107-1-james.morse@arm.com/
> 
>  arch/arm64/kvm/hyp/entry.S | 14 ++++++++++----
>  1 file changed, 10 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/kvm/hyp/entry.S b/arch/arm64/kvm/hyp/entry.S
> index a5a4254314a1..c2de1a1faaf4 100644
> --- a/arch/arm64/kvm/hyp/entry.S
> +++ b/arch/arm64/kvm/hyp/entry.S
> @@ -161,18 +161,24 @@ alternative_if ARM64_HAS_RAS_EXTN
>  	orr	x0, x0, #(1<<ARM_EXIT_WITH_SERROR_BIT)
>  1:	ret
>  alternative_else
> -	// If we have a pending asynchronous abort, now is the
> -	// time to find out. From your VAXorcist book, page 666:
> +	dsb	sy		// Synchronize against in-flight ld/st
> +	mrs	x2, isr_el1

The CPU is allowed to perform a system register access before the DSB
completes if it doesn't have a side effect. Reading ISR_EL1 doesn't have
such side effect, so you could end-up missing the abort. An ISB after
DSB should cure that, but you'll need to verify that it doesn't make
things much worse than what we already have.

> +	and	x2, x2, #(1<<8)	// ISR_EL1.A
> +	cbnz	x2, 2f
> +	ret
> +
> +2:
> +	// We know we have a pending asynchronous abort, now is the
> +	// time to flush it out. From your VAXorcist book, page 666:
>  	// "Threaten me not, oh Evil one!  For I speak with
>  	// the power of DEC, and I command thee to show thyself!"
>  	mrs	x2, elr_el2
> +alternative_endif

Note that the ISB will push the MSR out of the alternative window, which
is a good thing! ;-)

>  	mrs	x3, esr_el2
>  	mrs	x4, spsr_el2
>  	mov	x5, x0
>  
> -	dsb	sy		// Synchronize against in-flight ld/st
>  	msr	daifclr, #4	// Unmask aborts
> -alternative_endif
>  
>  	// This is our single instruction exception window. A pending
>  	// SError is guaranteed to occur at the earliest when we unmask
> 

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...
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  parent reply index

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-10 16:30 James Morse
2019-06-10 16:38 ` Robin Murphy
2019-06-18 15:04   ` James Morse
2019-06-10 16:58 ` Marc Zyngier [this message]
2019-06-18 15:05   ` James Morse

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