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From: Andrew Murray <andrew.murray@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: marc.zyngier@arm.com, kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v9 4/5] KVM: arm/arm64: remove pmc->bitmask
Date: Mon, 17 Jun 2019 16:43:11 +0100
Message-ID: <20190617154311.GM20984@e119886-lin.cambridge.arm.com> (raw)
In-Reply-To: <5e18d747-1d82-8eed-ef1c-de86c5b3a7e7@arm.com>

On Thu, Jun 13, 2019 at 05:50:43PM +0100, Suzuki K Poulose wrote:
> 
> 
> On 13/06/2019 10:39, Andrew Murray wrote:
> > On Thu, Jun 13, 2019 at 08:30:51AM +0100, Julien Thierry wrote:
> > > Hi Andrew,
> > > 
> > > On 12/06/2019 20:04, Andrew Murray wrote:
> > > > We currently use pmc->bitmask to determine the width of the pmc - however
> > > > it's superfluous as the pmc index already describes if the pmc is a cycle
> > > > counter or event counter. The architecture clearly describes the widths of
> > > > these counters.
> > > > 
> > > > Let's remove the bitmask to simplify the code.
> > > > 
> > > > Signed-off-by: Andrew Murray <andrew.murray@arm.com>
> > > > ---
> > > >   include/kvm/arm_pmu.h |  1 -
> > > >   virt/kvm/arm/pmu.c    | 19 +++++++++----------
> > > >   2 files changed, 9 insertions(+), 11 deletions(-)
> > > > 
> > > > diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
> > > > index b73f31baca52..2f0e28dc5a9e 100644
> > > > --- a/include/kvm/arm_pmu.h
> > > > +++ b/include/kvm/arm_pmu.h
> > > > @@ -28,7 +28,6 @@
> > > >   struct kvm_pmc {
> > > >   	u8 idx;	/* index into the pmu->pmc array */
> > > >   	struct perf_event *perf_event;
> > > > -	u64 bitmask;
> > > >   };
> > > >   struct kvm_pmu {
> > > > diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
> > > > index ae1e886d4a1a..88ce24ae0b45 100644
> > > > --- a/virt/kvm/arm/pmu.c
> > > > +++ b/virt/kvm/arm/pmu.c
> > > > @@ -47,7 +47,10 @@ u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx)
> > > >   		counter += perf_event_read_value(pmc->perf_event, &enabled,
> > > >   						 &running);
> > > > -	return counter & pmc->bitmask;
> > > > +	if (select_idx != ARMV8_PMU_CYCLE_IDX)
> > > > +		counter = lower_32_bits(counter);
> > > 
> > > Shouldn't this depend on PMCR.LC as well? If PMCR.LC is clear we only
> > > want the lower 32bits of the cycle counter.
> > 
> > Yes that's correct. The hunk should look like this:
> > 
> > -       return counter & pmc->bitmask;
> > +       if (!(select_idx == ARMV8_PMU_CYCLE_IDX &&
> > +             __vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_LC))
> > +               counter = lower_32_bits(counter);
> > +
> > +       return counter;
> 
> May be you could add a macro :
> 
> #define vcpu_pmu_counter_is_64bit(vcpu, idx) ?

Yes I think a helper would be useful - though I'd prefer the name
'kvm_pmu_idx_is_long_cycle_counter'. This seems a little clearer as
you could otherwise argue that a chained counter is also 64 bits.

Thanks,

Andrew Murray


> 
> Cheers
> Suzuki
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Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-12 19:04 [PATCH v9 0/5] KVM: arm/arm64: add support for chained counters Andrew Murray
2019-06-12 19:04 ` [PATCH v9 1/5] KVM: arm/arm64: rename kvm_pmu_{enable/disable}_counter functions Andrew Murray
2019-06-12 19:04 ` [PATCH v9 2/5] KVM: arm/arm64: extract duplicated code to own function Andrew Murray
2019-06-12 19:04 ` [PATCH v9 3/5] KVM: arm/arm64: re-create event when setting counter value Andrew Murray
2019-06-12 19:04 ` [PATCH v9 4/5] KVM: arm/arm64: remove pmc->bitmask Andrew Murray
2019-06-13  7:30   ` Julien Thierry
2019-06-13  9:39     ` Andrew Murray
2019-06-13 16:50       ` Suzuki K Poulose
2019-06-17 15:43         ` Andrew Murray [this message]
2019-06-17 16:33           ` Suzuki K Poulose
2019-06-17 18:06             ` Andrew Murray
2019-06-12 19:04 ` [PATCH v9 5/5] KVM: arm/arm64: support chained PMU counters Andrew Murray
2019-06-14 12:08   ` Suzuki K Poulose

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