* [PATCH v2 1/5] arm64: Add ARM64_WORKAROUND_1319367 for all A57 and A72 versions
2019-10-19 9:55 [PATCH v2 0/5] arm64: KVM: Add workaround for errata 1319367 and 1319537 Marc Zyngier
@ 2019-10-19 9:55 ` Marc Zyngier
2019-10-19 9:55 ` [PATCH v2 2/5] arm64: KVM: Reorder system register restoration and stage-2 activation Marc Zyngier
` (3 subsequent siblings)
4 siblings, 0 replies; 13+ messages in thread
From: Marc Zyngier @ 2019-10-19 9:55 UTC (permalink / raw)
To: linux-arm-kernel, kvmarm, kvm; +Cc: Catalin Marinas, Will Deacon
Rework the EL2 vector hardening that is only selected for A57 and A72
so that the table can also be used for ARM64_WORKAROUND_1319367.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/kernel/cpu_errata.c | 13 ++++++++++---
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index f19fe4b9acc4..277e37b2a513 100644
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -52,7 +52,8 @@
#define ARM64_HAS_IRQ_PRIO_MASKING 42
#define ARM64_HAS_DCPODP 43
#define ARM64_WORKAROUND_1463225 44
+#define ARM64_WORKAROUND_1319367 45
-#define ARM64_NCAPS 45
+#define ARM64_NCAPS 46
#endif /* __ASM_CPUCAPS_H */
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index f593f4cffc0d..a7afa6d4a58f 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -623,9 +623,9 @@ check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope)
return (need_wa > 0);
}
-#ifdef CONFIG_HARDEN_EL2_VECTORS
+#if defined(CONFIG_HARDEN_EL2_VECTORS) || defined(CONFIG_ARM64_ERRATUM_1319367)
-static const struct midr_range arm64_harden_el2_vectors[] = {
+static const struct midr_range ca57_a72[] = {
MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
{},
@@ -819,7 +819,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
{
.desc = "EL2 vector hardening",
.capability = ARM64_HARDEN_EL2_VECTORS,
- ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors),
+ ERRATA_MIDR_RANGE_LIST(ca57_a72),
},
#endif
{
@@ -851,6 +851,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
.matches = has_cortex_a76_erratum_1463225,
},
+#endif
+#ifdef CONFIG_ARM64_ERRATUM_1319367
+ {
+ .desc = "ARM erratum 1319367",
+ .capability = ARM64_WORKAROUND_1319367,
+ ERRATA_MIDR_RANGE_LIST(ca57_a72),
+ },
#endif
{
}
--
2.20.1
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^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v2 2/5] arm64: KVM: Reorder system register restoration and stage-2 activation
2019-10-19 9:55 [PATCH v2 0/5] arm64: KVM: Add workaround for errata 1319367 and 1319537 Marc Zyngier
2019-10-19 9:55 ` [PATCH v2 1/5] arm64: Add ARM64_WORKAROUND_1319367 for all A57 and A72 versions Marc Zyngier
@ 2019-10-19 9:55 ` Marc Zyngier
2019-10-24 16:09 ` James Morse
2019-10-19 9:55 ` [PATCH v2 3/5] arm64: KVM: Disable EL1 PTW when invalidating S2 TLBs Marc Zyngier
` (2 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: Marc Zyngier @ 2019-10-19 9:55 UTC (permalink / raw)
To: linux-arm-kernel, kvmarm, kvm; +Cc: Catalin Marinas, Will Deacon
In order to prepare for handling erratum 1319367, we need to make
sure that all system registers (and most importantly the registers
configuring the virtual memory) are set before we enable stage-2
translation.
This results in a minor reorganisation of the load sequence, without
any functional change.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kvm/hyp/switch.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
index 3d3815020e36..69e10b29cbd0 100644
--- a/arch/arm64/kvm/hyp/switch.c
+++ b/arch/arm64/kvm/hyp/switch.c
@@ -605,18 +605,23 @@ int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu)
__sysreg_save_state_nvhe(host_ctxt);
- __activate_vm(kern_hyp_va(vcpu->kvm));
- __activate_traps(vcpu);
-
- __hyp_vgic_restore_state(vcpu);
- __timer_enable_traps(vcpu);
-
/*
* We must restore the 32-bit state before the sysregs, thanks
* to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
+ *
+ * Also, and in order to be able to deal with erratum #1319537 (A57)
+ * and #1319367 (A72), we must ensure that all VM-related sysreg are
+ * restored before we enable S2 translation.
*/
__sysreg32_restore_state(vcpu);
__sysreg_restore_state_nvhe(guest_ctxt);
+
+ __activate_vm(kern_hyp_va(vcpu->kvm));
+ __activate_traps(vcpu);
+
+ __hyp_vgic_restore_state(vcpu);
+ __timer_enable_traps(vcpu);
+
__debug_switch_to_guest(vcpu);
__set_guest_arch_workaround_state(vcpu);
--
2.20.1
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 2/5] arm64: KVM: Reorder system register restoration and stage-2 activation
2019-10-19 9:55 ` [PATCH v2 2/5] arm64: KVM: Reorder system register restoration and stage-2 activation Marc Zyngier
@ 2019-10-24 16:09 ` James Morse
0 siblings, 0 replies; 13+ messages in thread
From: James Morse @ 2019-10-24 16:09 UTC (permalink / raw)
To: Marc Zyngier; +Cc: kvm, Catalin Marinas, Will Deacon, kvmarm, linux-arm-kernel
Hi Marc,
On 19/10/2019 10:55, Marc Zyngier wrote:
> In order to prepare for handling erratum 1319367, we need to make
> sure that all system registers (and most importantly the registers
> configuring the virtual memory) are set before we enable stage-2
> translation.
>
> This results in a minor reorganisation of the load sequence, without
> any functional change.
Reviewed-by: James Morse <james.morse@arm.com>
Thanks,
James
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 3/5] arm64: KVM: Disable EL1 PTW when invalidating S2 TLBs
2019-10-19 9:55 [PATCH v2 0/5] arm64: KVM: Add workaround for errata 1319367 and 1319537 Marc Zyngier
2019-10-19 9:55 ` [PATCH v2 1/5] arm64: Add ARM64_WORKAROUND_1319367 for all A57 and A72 versions Marc Zyngier
2019-10-19 9:55 ` [PATCH v2 2/5] arm64: KVM: Reorder system register restoration and stage-2 activation Marc Zyngier
@ 2019-10-19 9:55 ` Marc Zyngier
2019-10-24 16:10 ` James Morse
2019-10-19 9:55 ` [PATCH v2 4/5] arm64: KVM: Prevent speculative S1 PTW when restoring vcpu context Marc Zyngier
2019-10-19 9:55 ` [PATCH v2 5/5] arm64: Enable and document ARM errata 1319367 and 1319537 Marc Zyngier
4 siblings, 1 reply; 13+ messages in thread
From: Marc Zyngier @ 2019-10-19 9:55 UTC (permalink / raw)
To: linux-arm-kernel, kvmarm, kvm; +Cc: Catalin Marinas, Will Deacon
When erratum 1319367 is being worked around, special care must
be taken not to allow the page table walker to populate TLBs
while we have the stage-2 translation enabled (which would otherwise
result in a bizare mix of the host S1 and the guest S2).
We enforce this by setting TCR_EL1.EPD{0,1} before restoring the S2
configuration, and clear the same bits after having disabled S2.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kvm/hyp/tlb.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c
index eb0efc5557f3..c2bc17ca6430 100644
--- a/arch/arm64/kvm/hyp/tlb.c
+++ b/arch/arm64/kvm/hyp/tlb.c
@@ -63,6 +63,22 @@ static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm,
static void __hyp_text __tlb_switch_to_guest_nvhe(struct kvm *kvm,
struct tlb_inv_context *cxt)
{
+ if (cpus_have_const_cap(ARM64_WORKAROUND_1319367)) {
+ u64 val;
+
+ /*
+ * For CPUs that are affected by ARM 1319367, we need to
+ * avoid a host Stage-1 walk while we have the guest's
+ * VMID set in the VTTBR in order to invalidate TLBs.
+ * We're guaranteed that the S1 MMU is enabled, so we can
+ * simply set the EPD bits to avoid any further TLB fill.
+ */
+ val = cxt->tcr = read_sysreg_el1(SYS_TCR);
+ val |= TCR_EPD1_MASK | TCR_EPD0_MASK;
+ write_sysreg_el1(val, SYS_TCR);
+ isb();
+ }
+
__load_guest_stage2(kvm);
isb();
}
@@ -100,6 +116,13 @@ static void __hyp_text __tlb_switch_to_host_nvhe(struct kvm *kvm,
struct tlb_inv_context *cxt)
{
write_sysreg(0, vttbr_el2);
+
+ if (cpus_have_const_cap(ARM64_WORKAROUND_1319367)) {
+ /* Ensure write of the host VMID */
+ isb();
+ /* Restore the host's TCR_EL1 */
+ write_sysreg_el1(cxt->tcr, SYS_TCR);
+ }
}
static void __hyp_text __tlb_switch_to_host(struct kvm *kvm,
--
2.20.1
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 3/5] arm64: KVM: Disable EL1 PTW when invalidating S2 TLBs
2019-10-19 9:55 ` [PATCH v2 3/5] arm64: KVM: Disable EL1 PTW when invalidating S2 TLBs Marc Zyngier
@ 2019-10-24 16:10 ` James Morse
0 siblings, 0 replies; 13+ messages in thread
From: James Morse @ 2019-10-24 16:10 UTC (permalink / raw)
To: Marc Zyngier; +Cc: kvm, Catalin Marinas, Will Deacon, kvmarm, linux-arm-kernel
Hi Marc,
On 19/10/2019 10:55, Marc Zyngier wrote:
> When erratum 1319367 is being worked around, special care must
> be taken not to allow the page table walker to populate TLBs
> while we have the stage-2 translation enabled (which would otherwise
> result in a bizare mix of the host S1 and the guest S2).
>
> We enforce this by setting TCR_EL1.EPD{0,1} before restoring the S2
> configuration, and clear the same bits after having disabled S2.
Reviewed-by: James Morse <james.morse@arm.com>
Thanks,
James
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 4/5] arm64: KVM: Prevent speculative S1 PTW when restoring vcpu context
2019-10-19 9:55 [PATCH v2 0/5] arm64: KVM: Add workaround for errata 1319367 and 1319537 Marc Zyngier
` (2 preceding siblings ...)
2019-10-19 9:55 ` [PATCH v2 3/5] arm64: KVM: Disable EL1 PTW when invalidating S2 TLBs Marc Zyngier
@ 2019-10-19 9:55 ` Marc Zyngier
2019-10-24 16:10 ` James Morse
2019-10-19 9:55 ` [PATCH v2 5/5] arm64: Enable and document ARM errata 1319367 and 1319537 Marc Zyngier
4 siblings, 1 reply; 13+ messages in thread
From: Marc Zyngier @ 2019-10-19 9:55 UTC (permalink / raw)
To: linux-arm-kernel, kvmarm, kvm; +Cc: Catalin Marinas, Will Deacon
When handling erratum 1319367, we must ensure that the page table
walker cannot parse the S1 page tables while the guest is in an
inconsistent state. This is done as follows:
On guest entry:
- TCR_EL1.EPD{0,1} are set, ensuring that no PTW can occur
- all system registers are restored, except for TCR_EL1 and SCTLR_EL1
- stage-2 is restored
- SCTLR_EL1 and TCR_EL1 are restored
On guest exit:
- SCTLR_EL1.M and TCR_EL1.EPD{0,1} are set, ensuring that no PTW can occur
- stage-2 is disabled
- All host system registers are restored
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kvm/hyp/switch.c | 31 ++++++++++++++++++++++++++++++
arch/arm64/kvm/hyp/sysreg-sr.c | 35 ++++++++++++++++++++++++++++++++--
2 files changed, 64 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
index 69e10b29cbd0..5765b17c38c7 100644
--- a/arch/arm64/kvm/hyp/switch.c
+++ b/arch/arm64/kvm/hyp/switch.c
@@ -118,6 +118,20 @@ static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu)
}
write_sysreg(val, cptr_el2);
+
+ if (cpus_have_const_cap(ARM64_WORKAROUND_1319367)) {
+ struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt;
+
+ isb();
+ /*
+ * At this stage, and thanks to the above isb(), S2 is
+ * configured and enabled. We can now restore the guest's S1
+ * configuration: SCTLR, and only then TCR.
+ */
+ write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR);
+ isb();
+ write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR);
+ }
}
static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)
@@ -156,6 +170,23 @@ static void __hyp_text __deactivate_traps_nvhe(void)
{
u64 mdcr_el2 = read_sysreg(mdcr_el2);
+ if (cpus_have_const_cap(ARM64_WORKAROUND_1319367)) {
+ u64 val;
+
+ /*
+ * Set the TCR and SCTLR registers in the exact opposite
+ * sequence as __activate_traps_nvhe (first prevent walks,
+ * then force the MMU on). A generous sprinkling of isb()
+ * ensure that things happen in this exact order.
+ */
+ val = read_sysreg_el1(SYS_TCR);
+ write_sysreg_el1(val | TCR_EPD1_MASK | TCR_EPD0_MASK, SYS_TCR);
+ isb();
+ val = read_sysreg_el1(SYS_SCTLR);
+ write_sysreg_el1(val | SCTLR_ELx_M, SYS_SCTLR);
+ isb();
+ }
+
__deactivate_traps_common();
mdcr_el2 &= MDCR_EL2_HPMN_MASK;
diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c
index 7ddbc849b580..fb97547bfa79 100644
--- a/arch/arm64/kvm/hyp/sysreg-sr.c
+++ b/arch/arm64/kvm/hyp/sysreg-sr.c
@@ -117,12 +117,26 @@ static void __hyp_text __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
{
write_sysreg(ctxt->sys_regs[MPIDR_EL1], vmpidr_el2);
write_sysreg(ctxt->sys_regs[CSSELR_EL1], csselr_el1);
- write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR);
+
+ if (!cpus_have_const_cap(ARM64_WORKAROUND_1319367)) {
+ write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR);
+ write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR);
+ } else if (!ctxt->__hyp_running_vcpu) {
+ /*
+ * Must only be done for guest registers, hence the context
+ * test. We'recoming from the host, so SCTLR.M is already
+ * set. Pairs with __activate_traps_nvhe().
+ */
+ write_sysreg_el1((ctxt->sys_regs[TCR_EL1] |
+ TCR_EPD1_MASK | TCR_EPD0_MASK),
+ SYS_TCR);
+ isb();
+ }
+
write_sysreg(ctxt->sys_regs[ACTLR_EL1], actlr_el1);
write_sysreg_el1(ctxt->sys_regs[CPACR_EL1], SYS_CPACR);
write_sysreg_el1(ctxt->sys_regs[TTBR0_EL1], SYS_TTBR0);
write_sysreg_el1(ctxt->sys_regs[TTBR1_EL1], SYS_TTBR1);
- write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR);
write_sysreg_el1(ctxt->sys_regs[ESR_EL1], SYS_ESR);
write_sysreg_el1(ctxt->sys_regs[AFSR0_EL1], SYS_AFSR0);
write_sysreg_el1(ctxt->sys_regs[AFSR1_EL1], SYS_AFSR1);
@@ -135,6 +149,23 @@ static void __hyp_text __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
write_sysreg(ctxt->sys_regs[PAR_EL1], par_el1);
write_sysreg(ctxt->sys_regs[TPIDR_EL1], tpidr_el1);
+ if (cpus_have_const_cap(ARM64_WORKAROUND_1319367) &&
+ ctxt->__hyp_running_vcpu) {
+ /*
+ * Must only be done for host registers, hence the context
+ * test. Pairs with __deactivate_traps_nvhe().
+ */
+ isb();
+ /*
+ * At this stage, and thanks to the above isb(), S2 is
+ * deconfigured and disabled. We can now restore the host's
+ * S1 configuration: SCTLR, and only then TCR.
+ */
+ write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR);
+ isb();
+ write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR);
+ }
+
write_sysreg(ctxt->gp_regs.sp_el1, sp_el1);
write_sysreg_el1(ctxt->gp_regs.elr_el1, SYS_ELR);
write_sysreg_el1(ctxt->gp_regs.spsr[KVM_SPSR_EL1],SYS_SPSR);
--
2.20.1
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 4/5] arm64: KVM: Prevent speculative S1 PTW when restoring vcpu context
2019-10-19 9:55 ` [PATCH v2 4/5] arm64: KVM: Prevent speculative S1 PTW when restoring vcpu context Marc Zyngier
@ 2019-10-24 16:10 ` James Morse
2019-10-26 10:20 ` Marc Zyngier
0 siblings, 1 reply; 13+ messages in thread
From: James Morse @ 2019-10-24 16:10 UTC (permalink / raw)
To: Marc Zyngier; +Cc: kvm, Catalin Marinas, Will Deacon, kvmarm, linux-arm-kernel
Hi Marc,
On 19/10/2019 10:55, Marc Zyngier wrote:
> When handling erratum 1319367, we must ensure that the page table
> walker cannot parse the S1 page tables while the guest is in an
> inconsistent state. This is done as follows:
>
> On guest entry:
> - TCR_EL1.EPD{0,1} are set, ensuring that no PTW can occur
> - all system registers are restored, except for TCR_EL1 and SCTLR_EL1
> - stage-2 is restored
> - SCTLR_EL1 and TCR_EL1 are restored
>
> On guest exit:
> - SCTLR_EL1.M and TCR_EL1.EPD{0,1} are set, ensuring that no PTW can occur
> - stage-2 is disabled
> - All host system registers are restored
Reviewed-by: James Morse <james.morse@arm.com>
(whitespace nit below)
> diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
> index 69e10b29cbd0..5765b17c38c7 100644
> --- a/arch/arm64/kvm/hyp/switch.c
> +++ b/arch/arm64/kvm/hyp/switch.c
> @@ -118,6 +118,20 @@ static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu)
> }
>
> write_sysreg(val, cptr_el2);
> +
> + if (cpus_have_const_cap(ARM64_WORKAROUND_1319367)) {
> + struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt;
> +
> + isb();
> + /*
> + * At this stage, and thanks to the above isb(), S2 is
> + * configured and enabled. We can now restore the guest's S1
> + * configuration: SCTLR, and only then TCR.
> + */
(note for my future self: because the guest may have had M=0 and rubbish in the TTBRs)
> + write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR);
> + isb();
> + write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR);
> + }
> }
>
> diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c
> index 7ddbc849b580..fb97547bfa79 100644
> --- a/arch/arm64/kvm/hyp/sysreg-sr.c
> +++ b/arch/arm64/kvm/hyp/sysreg-sr.c
> @@ -117,12 +117,26 @@ static void __hyp_text __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
> {
> write_sysreg(ctxt->sys_regs[MPIDR_EL1], vmpidr_el2);
> write_sysreg(ctxt->sys_regs[CSSELR_EL1], csselr_el1);
> - write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR);
> +
> + if (!cpus_have_const_cap(ARM64_WORKAROUND_1319367)) {
> + write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR);
> + write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR);
> + } else if (!ctxt->__hyp_running_vcpu) {
> + /*
> + * Must only be done for guest registers, hence the context
> + * test. We'recoming from the host, so SCTLR.M is already
(Nit: We'recoming?)
> + * set. Pairs with __activate_traps_nvhe().
> + */
> + write_sysreg_el1((ctxt->sys_regs[TCR_EL1] |
> + TCR_EPD1_MASK | TCR_EPD0_MASK),
> + SYS_TCR);
> + isb();
> + }
Thanks,
James
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v2 4/5] arm64: KVM: Prevent speculative S1 PTW when restoring vcpu context
2019-10-24 16:10 ` James Morse
@ 2019-10-26 10:20 ` Marc Zyngier
2019-10-28 10:32 ` Catalin Marinas
0 siblings, 1 reply; 13+ messages in thread
From: Marc Zyngier @ 2019-10-26 10:20 UTC (permalink / raw)
To: James Morse, Catalin Marinas, Will Deacon; +Cc: kvm, linux-arm-kernel, kvmarm
On Thu, 24 Oct 2019 17:10:44 +0100,
James Morse <james.morse@arm.com> wrote:
Hi James,
> Hi Marc,
>
> On 19/10/2019 10:55, Marc Zyngier wrote:
> > When handling erratum 1319367, we must ensure that the page table
> > walker cannot parse the S1 page tables while the guest is in an
> > inconsistent state. This is done as follows:
> >
> > On guest entry:
> > - TCR_EL1.EPD{0,1} are set, ensuring that no PTW can occur
> > - all system registers are restored, except for TCR_EL1 and SCTLR_EL1
> > - stage-2 is restored
> > - SCTLR_EL1 and TCR_EL1 are restored
> >
> > On guest exit:
> > - SCTLR_EL1.M and TCR_EL1.EPD{0,1} are set, ensuring that no PTW can occur
> > - stage-2 is disabled
> > - All host system registers are restored
>
> Reviewed-by: James Morse <james.morse@arm.com>
>
> (whitespace nit below)
>
>
> > diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
> > index 69e10b29cbd0..5765b17c38c7 100644
> > --- a/arch/arm64/kvm/hyp/switch.c
> > +++ b/arch/arm64/kvm/hyp/switch.c
> > @@ -118,6 +118,20 @@ static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu)
> > }
> >
> > write_sysreg(val, cptr_el2);
> > +
> > + if (cpus_have_const_cap(ARM64_WORKAROUND_1319367)) {
> > + struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt;
> > +
> > + isb();
> > + /*
> > + * At this stage, and thanks to the above isb(), S2 is
> > + * configured and enabled. We can now restore the guest's S1
> > + * configuration: SCTLR, and only then TCR.
> > + */
>
> (note for my future self: because the guest may have had M=0 and rubbish in the TTBRs)
>
> > + write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR);
> > + isb();
> > + write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR);
> > + }
> > }
> >
>
>
> > diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c
> > index 7ddbc849b580..fb97547bfa79 100644
> > --- a/arch/arm64/kvm/hyp/sysreg-sr.c
> > +++ b/arch/arm64/kvm/hyp/sysreg-sr.c
> > @@ -117,12 +117,26 @@ static void __hyp_text __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
> > {
> > write_sysreg(ctxt->sys_regs[MPIDR_EL1], vmpidr_el2);
> > write_sysreg(ctxt->sys_regs[CSSELR_EL1], csselr_el1);
> > - write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR);
> > +
> > + if (!cpus_have_const_cap(ARM64_WORKAROUND_1319367)) {
> > + write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR);
> > + write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR);
> > + } else if (!ctxt->__hyp_running_vcpu) {
> > + /*
> > + * Must only be done for guest registers, hence the context
> > + * test. We'recoming from the host, so SCTLR.M is already
>
> (Nit: We'recoming?)
Well spotted, now fixed. And thanks for the reviewing, much appreciated.
Catalin, Will: given that this series conflicts with the workaround for
erratum 1542419, do you mind taking it via the arm64 tree?
To make things a bit simpler, I've updated the series with James' tags at
[1], and pushed out a resolution of the merge with arm64/for-next/core [2].
Thanks,
M.
[1] git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git kvm-arm64/erratum-1319367
[2] git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git kvm-arm64/erratum-1319367-resolved
--
Jazz is not dead, it just smells funny.
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v2 4/5] arm64: KVM: Prevent speculative S1 PTW when restoring vcpu context
2019-10-26 10:20 ` Marc Zyngier
@ 2019-10-28 10:32 ` Catalin Marinas
2019-10-28 10:49 ` Marc Zyngier
0 siblings, 1 reply; 13+ messages in thread
From: Catalin Marinas @ 2019-10-28 10:32 UTC (permalink / raw)
To: Marc Zyngier; +Cc: kvm, Will Deacon, kvmarm, linux-arm-kernel
On Sat, Oct 26, 2019 at 11:20:35AM +0100, Marc Zyngier wrote:
> Catalin, Will: given that this series conflicts with the workaround for
> erratum 1542419, do you mind taking it via the arm64 tree?
I assume you target 5.5 with this workaround.
I don't mind merging it but if you want to queue it, we already have a
stable for-next/neoverse-n1-stale-instr branch with 1542419 (I'll push a
fixup on top soon for a clang warning). The other issue is that we get a
conflict with mainline due to the tx2 erratum. If it gets too
complicated, I'll also merge for-next/fixes into for-next/core.
--
Catalin
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 4/5] arm64: KVM: Prevent speculative S1 PTW when restoring vcpu context
2019-10-28 10:32 ` Catalin Marinas
@ 2019-10-28 10:49 ` Marc Zyngier
2019-10-28 11:06 ` Catalin Marinas
0 siblings, 1 reply; 13+ messages in thread
From: Marc Zyngier @ 2019-10-28 10:49 UTC (permalink / raw)
To: Catalin Marinas; +Cc: kvm, Will Deacon, kvmarm, linux-arm-kernel
On Mon, 28 Oct 2019 10:32:17 +0000,
Catalin Marinas <catalin.marinas@arm.com> wrote:
Hi Catalin,
> On Sat, Oct 26, 2019 at 11:20:35AM +0100, Marc Zyngier wrote:
> > Catalin, Will: given that this series conflicts with the workaround for
> > erratum 1542419, do you mind taking it via the arm64 tree?
>
> I assume you target 5.5 with this workaround.
Absolutely. I'm happy to look at backports once this is in.
> I don't mind merging it but if you want to queue it, we already have
> a stable for-next/neoverse-n1-stale-instr branch with 1542419 (I'll
> push a fixup on top soon for a clang warning). The other issue is
> that we get a conflict with mainline due to the tx2 erratum. If it
> gets too complicated, I'll also merge for-next/fixes into
> for-next/core.
OK, let me have another look at providing a resolution that includes
all of the above. Worse case, you'll be able to pull the branch
directly.
Thanks,
M.
--
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 4/5] arm64: KVM: Prevent speculative S1 PTW when restoring vcpu context
2019-10-28 10:49 ` Marc Zyngier
@ 2019-10-28 11:06 ` Catalin Marinas
0 siblings, 0 replies; 13+ messages in thread
From: Catalin Marinas @ 2019-10-28 11:06 UTC (permalink / raw)
To: Marc Zyngier; +Cc: kvm, Will Deacon, kvmarm, linux-arm-kernel
On Mon, Oct 28, 2019 at 10:49:37AM +0000, Marc Zyngier wrote:
> On Mon, 28 Oct 2019 10:32:17 +0000,
> Catalin Marinas <catalin.marinas@arm.com> wrote:
> > On Sat, Oct 26, 2019 at 11:20:35AM +0100, Marc Zyngier wrote:
> > > Catalin, Will: given that this series conflicts with the workaround for
> > > erratum 1542419, do you mind taking it via the arm64 tree?
[...]
> > I don't mind merging it but if you want to queue it, we already have
> > a stable for-next/neoverse-n1-stale-instr branch with 1542419 (I'll
> > push a fixup on top soon for a clang warning). The other issue is
> > that we get a conflict with mainline due to the tx2 erratum. If it
> > gets too complicated, I'll also merge for-next/fixes into
> > for-next/core.
>
> OK, let me have another look at providing a resolution that includes
> all of the above. Worse case, you'll be able to pull the branch
> directly.
Don't worry about the resolution, I'll fix it up myself when merging
into for-next/core. The latter is not a stable branch, just an octopus
merge of various for-next/* topic branches.
--
Catalin
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 5/5] arm64: Enable and document ARM errata 1319367 and 1319537
2019-10-19 9:55 [PATCH v2 0/5] arm64: KVM: Add workaround for errata 1319367 and 1319537 Marc Zyngier
` (3 preceding siblings ...)
2019-10-19 9:55 ` [PATCH v2 4/5] arm64: KVM: Prevent speculative S1 PTW when restoring vcpu context Marc Zyngier
@ 2019-10-19 9:55 ` Marc Zyngier
4 siblings, 0 replies; 13+ messages in thread
From: Marc Zyngier @ 2019-10-19 9:55 UTC (permalink / raw)
To: linux-arm-kernel, kvmarm, kvm; +Cc: Catalin Marinas, Will Deacon
Now that everything is in place, let's get the ball rolling
by allowing the corresponding config option to be selected.
Also add the required information to silicon_errata.rst.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
Documentation/arm64/silicon-errata.rst | 4 ++++
arch/arm64/Kconfig | 10 ++++++++++
2 files changed, 14 insertions(+)
diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index 17ea3fecddaa..0808be134fce 100644
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -70,8 +70,12 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
+----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-A57 | #1319537 | ARM64_ERRATUM_1319367 |
++----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A72 | #853709 | N/A |
+----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-A72 | #1319367 | ARM64_ERRATUM_1319367 |
++----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 |
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 950a56b71ff0..b2877ed09307 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -538,6 +538,16 @@ config ARM64_ERRATUM_1286807
invalidated has been observed by other observers. The
workaround repeats the TLBI+DSB operation.
+config ARM64_ERRATUM_1319367
+ bool "Cortex-A57/A72: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
+ default y
+ help
+ This option adds work arounds for ARM Cortex-A57 erratum 1319537
+ and A72 erratum 1319367
+
+ Cortex-A57 and A72 cores could end-up with corrupted TLBs by
+ speculating an AT instruction during a guest context switch.
+
If unsure, say Y.
config ARM64_ERRATUM_1463225
--
2.20.1
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^ permalink raw reply related [flat|nested] 13+ messages in thread