From: Andrew Murray <andrew.murray@arm.com>
To: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Cc: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v1 2/3] KVM: arm64: limit PMU version to ARMv8.4
Date: Fri, 25 Oct 2019 15:52:18 +0100 [thread overview]
Message-ID: <20191025145219.28350-3-andrew.murray@arm.com> (raw)
In-Reply-To: <20191025145219.28350-1-andrew.murray@arm.com>
ARMv8.5-PMU introduces 64-bit event counters, however KVM doesn't yet
support this. Let's trap the Debug Feature Registers in order to limit
PMUVer/PerfMon in the Debug Feature Registers to PMUv3 for ARMv8.4.
Signed-off-by: Andrew Murray <andrew.murray@arm.com>
---
arch/arm64/include/asm/sysreg.h | 4 ++++
arch/arm64/kvm/sys_regs.c | 36 +++++++++++++++++++++++++++++++--
2 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 972d196c7714..0e82e210e22b 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -672,6 +672,10 @@
#define ID_AA64DFR0_TRACEVER_SHIFT 4
#define ID_AA64DFR0_DEBUGVER_SHIFT 0
+#define ID_DFR0_PERFMON_SHIFT 24
+
+#define ID_DFR0_EL1_PMUVER_8_4 5
+
#define ID_ISAR5_RDM_SHIFT 24
#define ID_ISAR5_CRC32_SHIFT 16
#define ID_ISAR5_SHA2_SHIFT 12
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 2071260a275b..829838c9af3f 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -666,6 +666,37 @@ static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
}
+static bool access_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
+ struct sys_reg_params *p,
+ const struct sys_reg_desc *rd)
+{
+ if (p->is_write)
+ return write_to_read_only(vcpu, p, rd);
+
+ /* Limit guests to PMUv3 for ARMv8.4 */
+ p->regval = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
+ p->regval = cpuid_feature_cap_signed_field_width(p->regval,
+ ID_AA64DFR0_PMUVER_SHIFT,
+ 4, ID_DFR0_EL1_PMUVER_8_4);
+
+ return p->regval;
+}
+
+static bool access_id_dfr0_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *rd)
+{
+ if (p->is_write)
+ return write_to_read_only(vcpu, p, rd);
+
+ /* Limit guests to PMUv3 for ARMv8.4 */
+ p->regval = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1);
+ p->regval = cpuid_feature_cap_signed_field_width(p->regval,
+ ID_DFR0_PERFMON_SHIFT,
+ 4, ID_DFR0_EL1_PMUVER_8_4);
+
+ return p->regval;
+}
+
static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
@@ -1405,7 +1436,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
/* CRm=1 */
ID_SANITISED(ID_PFR0_EL1),
ID_SANITISED(ID_PFR1_EL1),
- ID_SANITISED(ID_DFR0_EL1),
+ { SYS_DESC(SYS_ID_DFR0_EL1), access_id_dfr0_el1 },
+
ID_HIDDEN(ID_AFR0_EL1),
ID_SANITISED(ID_MMFR0_EL1),
ID_SANITISED(ID_MMFR1_EL1),
@@ -1444,7 +1476,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
ID_UNALLOCATED(4,7),
/* CRm=5 */
- ID_SANITISED(ID_AA64DFR0_EL1),
+ { SYS_DESC(SYS_ID_AA64DFR0_EL1), access_id_aa64dfr0_el1 },
ID_SANITISED(ID_AA64DFR1_EL1),
ID_UNALLOCATED(5,2),
ID_UNALLOCATED(5,3),
--
2.21.0
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next prev parent reply other threads:[~2019-10-25 14:52 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-25 14:52 [PATCH v1 0/3] arm64: perf: Add support for ARMv8.5-PMU 64-bit counters Andrew Murray
2019-10-25 14:52 ` [PATCH v1 1/3] arm64: cpufeature: Extract capped fields Andrew Murray
2019-10-25 14:52 ` Andrew Murray [this message]
2019-10-25 14:52 ` [PATCH v1 3/3] arm64: perf: Add support for ARMv8.5-PMU 64-bit counters Andrew Murray
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