From: Andre Przywara <andre.przywara@arm.com> To: Andrew Jones <drjones@redhat.com>, Paolo Bonzini <pbonzini@redhat.com> Cc: Marc Zyngier <maz@kernel.org>, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Subject: [kvm-unit-tests PATCH 09/17] arm: gic: Add test for flipping GICD_CTLR.DS Date: Fri, 8 Nov 2019 14:42:32 +0000 Message-ID: <20191108144240.204202-10-andre.przywara@arm.com> (raw) In-Reply-To: <20191108144240.204202-1-andre.przywara@arm.com> The DS (Disable Security) bit in the GICv3 GICD_CTLR register controls access to Group 0 interrupts from the non-secure side. The KVM VGIC emulation provides a "GIC with a single security state", so both groups should be accessible. Provide a test to check this bit can be set to one. The current KVM emulation should treat this is as RAO/WI (which we also check here). It would be architecturally compliant though to have this bit at 0 as well, so we refrain from treating different behaviour as a FAIL. However we use this as a gateway for further Group 0 IRQ tests. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- arm/gic.c | 62 ++++++++++++++++++++++++++++++++++++++++++++ lib/arm/asm/gic-v3.h | 1 + 2 files changed, 63 insertions(+) diff --git a/arm/gic.c b/arm/gic.c index 304b7b9..c882a24 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -531,6 +531,8 @@ static void gic_test_mmio(void) reg = readl(gic_dist_base + GICD_TYPER); nr_irqs = GICD_TYPER_IRQS(reg); report_info("number of implemented SPIs: %d", nr_irqs - GIC_FIRST_SPI); + report_info("GIC %s security extension", + reg & (1U << 10) ? "has" : "does not have"); if (gic_version() == 0x2) test_typer_v2(reg); @@ -638,6 +640,60 @@ static void spi_test_smp(void) report("SPI delievered on all cores", cores == nr_cpus); } +/* + * Check the security state configuration of the GIC. + * Test whether we can switch to a single security state, to test both + * group 0 and group 1 interrupts. + * Architecturally a GIC can be configured in different ways, so we don't + * insist on the current way KVM emulates the GIC. + */ +static bool gicv3_check_security(void *gicd_base) +{ + u32 ctlr = readl(gicd_base + GICD_CTLR); + + if (ctlr & GICD_CTLR_DS) { + writel(ctlr & ~GICD_CTLR_DS, gicd_base + GICD_CTLR); + ctlr = readl(gicd_base + GICD_CTLR); + if (!(ctlr & GICD_CTLR_DS)) + report_info("GIC allowing two security states"); + else + report_info("GIC is one security state only"); + } else { + report_info("GIC resets to two security states"); + } + + writel(ctlr | GICD_CTLR_DS, gicd_base + GICD_CTLR); + ctlr = readl(gicd_base + GICD_CTLR); + report("switching to single security state", ctlr & GICD_CTLR_DS); + + /* Group0 delivery only works in single security state. */ + return ctlr & GICD_CTLR_DS; +} + +/* + * The GIC architecture describes two interrupt groups, group 0 and group 1. + * On bare-metal systems, running in non-secure world on a GIC with the + * security extensions, there is only one group available: group 1. + * However in the kernel KVM emulates a GIC with only one security state, + * so both groups are available to guests. + * Check whether this works as expected (as Linux will not use this feature). + * We can only verify this state on a GICv3, so we check it there and silently + * assume it's valid for GICv2. + */ +static void test_irq_group(void *gicd_base) +{ + bool is_gicv3 = (gic_version() == 3); + + report_prefix_push("GROUP"); + gic_enable_defaults(); + + if (is_gicv3) { + /* GICv3 features a bit to read and set the security state. */ + if (!gicv3_check_security(gicd_base)) + return; + } +} + static void spi_send(void) { irqs_enable(); @@ -647,6 +703,12 @@ static void spi_send(void) if (nr_cpus > 1) spi_test_smp(); + if (gic_version() == 3) + test_irq_group(gicv3_dist_base()); + + if (gic_version() == 2) + test_irq_group(gicv2_dist_base()); + check_spurious(); exit(report_summary()); } diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index 8cfaed1..2eaf944 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -19,6 +19,7 @@ * group1 enable bits with respect to that view. */ #define GICD_CTLR_RWP (1U << 31) +#define GICD_CTLR_DS (1U << 6) #define GICD_CTLR_ARE_NS (1U << 4) #define GICD_CTLR_ENABLE_G1A (1U << 1) #define GICD_CTLR_ENABLE_G1 (1U << 0) -- 2.17.1 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
next prev parent reply index Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-08 14:42 [kvm-unit-tests PATCH 00/17] arm: gic: Test SPIs and interrupt groups Andre Przywara 2019-11-08 14:42 ` [kvm-unit-tests PATCH 01/17] arm: gic: Enable GIC MMIO tests for GICv3 as well Andre Przywara 2019-11-08 17:28 ` Alexandru Elisei 2019-11-12 12:49 ` Auger Eric 2019-11-08 14:42 ` [kvm-unit-tests PATCH 02/17] arm: gic: Generalise function names Andre Przywara 2019-11-12 11:11 ` Alexandru Elisei 2019-11-12 12:49 ` Auger Eric 2019-11-08 14:42 ` [kvm-unit-tests PATCH 03/17] arm: gic: Provide per-IRQ helper functions Andre Przywara 2019-11-12 12:51 ` Alexandru Elisei 2019-11-12 15:53 ` Auger Eric 2019-11-12 16:53 ` Alexandru Elisei 2019-11-12 13:49 ` Auger Eric 2019-11-08 14:42 ` [kvm-unit-tests PATCH 04/17] arm: gic: Support no IRQs test case Andre Przywara 2019-11-12 13:26 ` Alexandru Elisei 2019-11-12 21:14 ` Auger Eric 2019-11-08 14:42 ` [kvm-unit-tests PATCH 05/17] arm: gic: Prepare IRQ handler for handling SPIs Andre Przywara 2019-11-12 13:36 ` Alexandru Elisei 2019-11-12 20:56 ` Auger Eric 2019-11-08 14:42 ` [kvm-unit-tests PATCH 06/17] arm: gic: Add simple shared IRQ test Andre Przywara 2019-11-12 13:54 ` Alexandru Elisei 2019-11-08 14:42 ` [kvm-unit-tests PATCH 07/17] arm: gic: Extend check_acked() to allow silent call Andre Przywara 2019-11-12 15:23 ` Alexandru Elisei 2019-11-14 12:32 ` Andrew Jones 2019-11-15 11:32 ` Alexandru Elisei 2019-11-08 14:42 ` [kvm-unit-tests PATCH 08/17] arm: gic: Add simple SPI MP test Andre Przywara 2019-11-12 15:41 ` Alexandru Elisei 2019-11-08 14:42 ` Andre Przywara [this message] 2019-11-12 16:42 ` [kvm-unit-tests PATCH 09/17] arm: gic: Add test for flipping GICD_CTLR.DS Alexandru Elisei 2019-11-14 13:39 ` Vladimir Murzin 2019-11-14 14:17 ` Andre Przywara 2019-11-14 14:50 ` Vladimir Murzin 2019-11-14 15:21 ` Alexandru Elisei 2019-11-14 15:27 ` Peter Maydell 2019-11-14 15:47 ` Alexandru Elisei 2019-11-14 15:56 ` Peter Maydell 2019-11-08 14:42 ` [kvm-unit-tests PATCH 10/17] arm: gic: Check for writable IGROUPR registers Andre Przywara 2019-11-12 16:51 ` Alexandru Elisei 2019-11-08 14:42 ` [kvm-unit-tests PATCH 11/17] arm: gic: Check for validity of both group enable bits Andre Przywara 2019-11-12 16:58 ` Alexandru Elisei 2019-11-08 14:42 ` [kvm-unit-tests PATCH 12/17] arm: gic: Change gic_read_iar() to take group parameter Andre Przywara 2019-11-12 17:19 ` Alexandru Elisei 2019-11-14 12:50 ` Andrew Jones 2019-11-08 14:42 ` [kvm-unit-tests PATCH 13/17] arm: gic: Change write_eoir() " Andre Przywara 2019-11-08 14:42 ` [kvm-unit-tests PATCH 14/17] arm: gic: Prepare for receiving GIC group 0 interrupts via FIQs Andre Przywara 2019-11-12 17:30 ` Alexandru Elisei 2019-11-08 14:42 ` [kvm-unit-tests PATCH 15/17] arm: gic: Provide FIQ handler Andre Przywara 2019-11-13 10:14 ` Alexandru Elisei 2019-11-08 14:42 ` [kvm-unit-tests PATCH 16/17] arm: gic: Prepare interrupt statistics for both groups Andre Przywara 2019-11-13 10:44 ` Alexandru Elisei 2019-11-08 14:42 ` [kvm-unit-tests PATCH 17/17] arm: gic: Test Group0 SPIs Andre Przywara 2019-11-13 11:26 ` Alexandru Elisei
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